hl186.txt

mcs51,2051,x86系列MCU

HILITES.TXT
#ICU 80C186EA#
#ICU 80C186XL#
Programmable Interrupt Control Unit\n
 - Four external maskable interrupt inputs\n
 - Supports up to 128 interrupts with cascaded 82C59s\n
 - Five internal peripheral interrupt sources\n
 - One independent non-maskable interrupt input\n
#ICU 80C186EB#
Programmable Interrupt Control Unit\n
 - Five external maskable interrupt inputs\n
 - Supports up to 128 interrupts with cascaded 82C59s\n
 - Five internal peripheral interrupt sources\n
 - One independent non-maskable interrupt input\n
#ICU 80C186EC#
Programmable Interrupt Control Unit\n
 - Eight external maskable interrupt request inputs\n
 - Supports up to 57 interrupts with cascaded 82C59s\n
 - Eleven internal peripheral interrupt sources\n
 - 8259A compatible\n
#WDT 80C186EC#
Watchdog Timer\n
 - 32-bit timer\n
 - Allows recovery from system upsets\n
 - Usable as a general-purpose timer\n
#Clock 80C186EA#
#Clock 80C186XL#
#Clock 80C186EB#
#Clock 80C186EC#
Clock\n
 - 0 to 20 MHz operation at 5 volts\n
 - 0 to 13 MHz operation at 3 volts\n
 - 50% duty cycle\n
 - Static design\n
#Timer 80C186EA#
#Timer 80C186XL#
#Timer 80C186EB#
#Timer 80C186EC#
Timer Counter Unit\n
 - Three independent 16-bit timers available\n
 - Timers 0 and 1 can count internal or external events\n
 - Timers 0 and 1 outputs available\n
 - Timer 2 counts internal clocks\n
 - Timers can be cascaded to create 32- or 48-bit timers\n
 - Timers can be programmed to interrupt at time-out\n
#DMA 80C186EA#
#DMA 80C186XL#
Direct Memory Access\n
 - Two independent DMA channels\n
 - Access memory and I/O\n
 - 64K block transfers\n
 - External request pin\n
 - Internal requests (timer)\n
 - Software requests\n
 - 20-bit source and destination pointers\n
 - Byte/word transfers\n
#DMA 80C186EC#
Direct Memory Access\n
 - Four independent DMA channels\n
 - Access memory and I/O\n
 - 64K block transfers\n
 - External request pin\n
 - Internal requests (timer and CSU)\n
 - Software requests\n
 - 20-bit source and destination pointers\n
 - Byte/word transfers\n
#PM 80C186EA#
Power Management\n
   Idle mode\n
    - Freezes CPU clock, peripherals remain active\n
    - Reduces power by approximately 30%\n
    - Exited via unmasked interrupt\n
\n
   Powerdown mode\n
    - Freezes all internal clocks\n
    - Reduces current to leakage (uA)\n
    - Wake-up by NMI or reset\n
\n
   Powersave mode\n
    - Programmable clock divisor (1, 4, 8, and 16)\n
    - Icc scales linearly with frequency\n
#PM 80C186EB#
Power Management\n
   Idle mode\n
    - Freezes CPU clock, peripherals remain active\n
    - Reduces power by approximately 30%\n
    - Exited via unmasked interrupt\n
\n
   Powerdown mode\n
    - Freezes all internal clocks\n
    - Reduces current to leakage (uA)\n
    - Wake-up by NMI or reset\n
#PM 80C186EC#
Power Management\n
   Idle mode\n
    - Freezes CPU clock, peripherals remain active\n
    - Reduces power by approximately 30%\n
    - Exited via unmasked interrupt\n
\n
   Powerdown mode\n
    - Freezes all internal clocks\n
    - Reduces current to leakage (uA)\n
    - Wake-up by NMI, reset, or unmasked external interrupts\n
\n
   Powersave mode\n
    - Programmable clock divisor (1, 4, 8, 16, 32, and 64)\n
    - Icc scales linearly with frequency\n
#CPU 80C186EA#
#CPU 80C186XL#
CPU\n
 - Static CPU core\n
 - Full CMOS I/O XL has TTL-compatible inputs\n
 - Object code compatible with 8086/88\n
 - Expanded 8086 instruction set\n
 - Performance:\n
    ~ 1.1 MIPS @ 20 MHz\n
    ~ 387 KWhetstones with 80C187 coprocessor\n
    ~ 2000 Dhrystones\n
 - 68 PGA, 68 LCC, 68 PLCC, 80 QFP, 80 SQFP\n
#CPU 80C186EB#
CPU\n
 - Static CPU core\n
 - Full CMOS I/O\n
 - Object code compatible with 8086/88\n
 - Expanded 8086 instruction set\n
 - Performance:\n
    ~ 1.1 MIPS @ 20 MHz\n
    ~ 387 KWhetstones with 80C187 coprocessor\n
    ~ 2000 Dhrystones\n
 - 84 PLCC, 80 QFP, 80 SQFP\n
#CPU 80C186EC#
CPU\n
 - Static CPU core\n
 - Full CMOS I/O\n
 - Object code compatible with 8086\n
 - Expanded 8086 instruction set\n
 - Performance:\n
    ~ 1.1 MIPS @ 20 MHz\n
    ~ 387 KWhetstones with 80C187 coprocessor\n
    ~ 2000 Dhrystones\n
 - 100 QFP-EIAJ, 100 QFP-JEDEC\n
#BIU 80C186EA#
#BIU 80C186XL#
#BIU 80C186EB#
#BIU 80C186EC#
Bus Interface Unit\n
 - 1 Mbyte memory address range\n
 - 64 Kbyte I/O address range\n
 - 8- and 16-bit external data bus versions\n
#CSU 80C186EA#
#CSU 80C186XL#
Chip Select Unit\n
 - 13 programmable memory and peripheral chip selects\n
 - Replaces address decoding logic\n
 - Replaces READY generation logic\n
 - Programmable wait states (0-3)\n
#CSU 80C186EC#
#CSU 80C186EB#
Chip Select Unit\n
 - Ten programmable memory and peripheral chip selects\n
 - Replaces address decoding logic\n
 - Replaces READY generation logic\n
 - Programmable wait states (0-15)\n
 - Allows overlapping of chip selects\n
 - 10-bit start and stop address fields\n
 - Granularity of 1 Kbyte in memory address space\n
   or 64 bytes I/O address space\n
#RCU 80C186EA#
#RCU 80C186XL#
#RCU 80C186EB#
Refresh Control Unit\n
 - Provides periodic DRAM refresh cycles\n
 - Programmable refresh interval and starting address\n
 - Refresh 1-Mbit DRAMs\n
#RCU 80C186EC#
Refresh Control Unit\n
 - Provides periodic DRAM refresh cycles\n
 - Programmable refresh interval and address range\n
 - Refresh 4-Mbit DRAMs\n
#PCB 80C186EA#
#PCB 80C186XL#
#PCB 80C186EB#
#PCB 80C186EC#
Peripheral Control Block\n
 - Peripheral control registers reside in 256-byte block\n
 - Can be located in either memory or I/O space\n
#FP 80C186EA#
#FP 80C186XL#
#FP 80C186EB#
#FP 80C186EC#
80C187\n
  Direct Numeric Interface\n
#IO 80C186EB#
I/O Ports\n
  Two flexible I/O ports (multiplexed function)\n
#IO 80C186EC#
I/O Ports\n
  Three flexible I/O ports (multiplexed function)\n
#Serial 80C186EB#
#Serial 80C186EC#
Serial Port\n
 - Two independent serial channels\n
 - Integral baud-rate generator\n
 - One synchronous mode\n
 - Four asynchronous modes\n
 - Double-buffered transmit/receive\n
 - Error detection\n
 - Can generate interrupt on transmit or receive\n