pe186.rd1

mcs51,2051,x86系列MCU

this field and the Decrement field are set (or cleared), the source address
will NOT change after a DMA transfer completes.
#DMA? 80C186?? 109#
Check this field to decrement the source address after a DMA transfer
completes, or clear this field to prevent the source address from being
decremented after a DMA transfer completes.

NOTE: To correctly specify that the source address decrement after a completed
transfer, you must set this field and clear the Increment field.  When both
this field and the Increment field are set (or cleared), the source address
will NOT change after a DMA transfer completes.
#DMA? 80C186?? 110#
Check this field to indicate that the destination address applies to memory
address space, or clear this field to indicate that the destination address
applies to I/O address space.
#DMA? 80C186?? 111#
Check this field to increment the destination address after a DMA transfer
completes, or clear this field to prevent the destination address from being
incremented after a DMA transfer completes.

NOTE: To correctly specify that the destination address increment after a
completed transfer, you must set this field and clear the Decrement field.
When both this field and the Decrement field are set (or cleared), the
destination address will NOT change after a DMA transfer completes.
#DMA? 80C186?? 112#
Check this field to decrement the destination address after a DMA transfer
completes, or clear this field to prevent the destination address from being
decremented after a DMA transfer completes.

NOTE: To correctly specify that the destination address decrement after a
completed transfer, you must set this field and clear the Increment field.
When both this field and the Increment field are set (or cleared), the
destination address will NOT change after a DMA transfer completes.
#DMA? 80C186?? 113#
Check this field to establish this DMA channel as higher priority over the
other DMA channel, or clear this field to have this DMA channel at the same or
lower priority than the other DMA channel.

A channel with higher priority is serviced first when both have a DMA request
active at the same time.
#DMA? 80C186?? 114#
Check this field to enable internal DMA requests, or clear this field to
enable external DMA requests.

Selecting one disables the other, meaning that you cannot enable both internal
and external requests.
#DMA? 80C186?? 115#
Check this field to halt DMA transfers when the Transfer Count register
reaches 0, or clear this field to allow unlimited DMA transfers to occur.

This field is ignored when Unsynchronized transfers has been specified.
#DMA? 80C186?? 116#
Check this field to generate an interrupt when the Transfer Count register
reaches 0, or clear this field to disable interrupts.

This field only applies when Terminal Count field has been checked, meaning
that the interrupt occurs only when the DMA channel has been halted.
#DMA? 80C186?? 117#
Check this field to enable (arm) the DMA channel, or clear this field to
disable (halt) the DMA channel.

NOTE: You must check the Change Start Bit field to enable or disable the DMA
channel.  Clearing the Change Start Bit field prevents a write operation from
modifying this field.

In Source or Destination Synchronization modes, checking this field arms the
DMA channel.  A DMA request (internal or external) will now cause a DMA
transfer to occur.

In Unsynchronized mode, checking this field immediately causes the DMA channel
to initiate a DMA transfer.  Transfers continue until the Terminal Count has
been reached (or an NMI is generated).
#DMA? 80C186?? 118#
Check this field to allow the Start field to be modified by a write operation,
or clear this field to prevent modification of the Start field during a write
operation.

Use this field to change DMA channel operation without affecting the state of
the Start field.
#DMA? 80C186?? 119#
Check this field to specify WORD-oriented DMA transfers, or clear this field
to specify BYTE-oriented DMA transfers.

When this field is checked, the source and destination address pointers will
count by two after each DMA transfer.  When this field is cleared, the source
and destination pointers will count by one after each DMA transfer.
#DMA? 80C186EC 120#
Check this field to have DMA Channels 0-1 at higher priority than DMA Channels
2-3, or clear this field to have DMA Channels 0-1 at the same or lower
priority than DMA Channels 2-3.
#DMA? 80C186EC 121#
Check this field to have DMA Channels 2-3 at higher priority than DMA Channels
0-1, or clear this field to have DMA Channels 2-3 at the same or lower
priority than DMA Channels 0-1.
#DMA? 80C186EC 122#
Check this field to select Serial Channel 0 as the source of internal DMA
requests, or clear this field to select Timer 2 as the source of internal DMA
requests.

Checking this field routes the transmit data complete interrupt to DMA Channel
0 and the receive data complete interrupt to DMA Channel 1.  When this field
is cleared, the Timer 2 interrupt is routed to both DMA channels.
#DMA? 80C186EC 123#
Check this field to select Serial Channel 1 as the source of internal DMA
requests, or clear this field to select Timer 2 as the source of internal DMA
requests.

Checking this field routes the transmit data complete interrupt to DMA Channel
2 and the receive data complete interrupt to DMA Channel 3.  When this field
is cleared, the Timer 2 interrupt is routed to both DMA channels.
#ICU 80C186EA 100#
#ICU 80C186XL 100#
#ICU 80C186EB 100#
#ICU 80C186EA 105#
#ICU 80C186XL 105#
#ICU 80C186EB 105#
#ICU 80C186EA 110#
#ICU 80C186XL 110#
#ICU 80C186EB 110#
#ICU 80C186EA 113#
#ICU 80C186XL 113#
#ICU 80C186EB 113#
Check this field to mask (disable) the interrupt, or clear this field to
unmask (enable) the interrupt.
#ICU 80C186EA 101#
#ICU 80C186XL 101#
#ICU 80C186EB 101#
#ICU 80C186EA 106#
#ICU 80C186XL 106#
#ICU 80C186EB 106#
#ICU 80C186EA 111#
#ICU 80C186XL 111#
#ICU 80C186EB 111#
#ICU 80C186EA 114#
#ICU 80C186XL 114#
#ICU 80C186EB 114#
Enter the priority level (0 to 7) for this interrupt.  0 is highest priority
and 7 is lowest priority.
#ICU 80C186EA 102#
#ICU 80C186XL 102#
#ICU 80C186EB 102#
#ICU 80C186EA 107#
#ICU 80C186XL 107#
#ICU 80C186EB 107#
#ICU 80C186EA 112#
#ICU 80C186XL 112#
#ICU 80C186EB 112#
#ICU 80C186EA 115#
#ICU 80C186XL 115#
#ICU 80C186EB 115#
Check this field to select LEVEL interrupt input triggering, or clear this
field to select EDGE interrupt input triggering.

In level triggering, an interrupt is generated whenever the input is at a high
(1) level.  In edge triggering, an interrupt is generated only when the input
makes a low-to-high transition.
#ICU 80C186EA 103#
#ICU 80C186XL 103#
#ICU 80C186EB 103#
#ICU 80C186EA 108#
#ICU 80C186XL 108#
#ICU 80C186EB 108#
Check this field to enable cascade mode, or clear this field to disable
cascade mode.

Cascade mode is used to expand the number of external interrupt sources.
#ICU 80C186EA 104#
#ICU 80C186XL 104#
#ICU 80C186EB 104#
#ICU 80C186EA 109#
#ICU 80C186XL 109#
#ICU 80C186EB 109#
Check this field to enable Special Fully Nested Mode, or clear this field to
disable the mode.

Special Fully Nested Mode allows an interrupt from this source to nest within
itself.  Otherwise, the interrupt would be blocked until its In Service bit
has been cleared (by issuing an End Of Interrupt).
#ICU 80C186EA 116#
#ICU 80C186XL 116#
#ICU 80C186EB 116#
Check this field to mask (disable) ALL Timer interrupts, or clear this field
to unmask (enable) Timer interrupts.

NOTE: All three Timers share a common interrupt input request, although each
Timer has its own interrupt vector.  Setting this field masks ALL Timer
interrupts.  To individually mask Timer interrupts, you must disable the Timer
Channel from generating the interrupt.
#ICU 80C186EA 117#
#ICU 80C186XL 117#
#ICU 80C186EB 117#
Enter the priority level (0 to 7) for ALL Timer interrupts.  0 is highest
priority and 7 is lowest priority.

NOTE: All three Timers share a common interrupt input request, although each
Timer has its own interrupt vector.  This field sets the priority of ALL Timer
interrupts relative to the other interrupt sources.  Each timer interrupt
has a fixed priority relative to the others.  Timer 0 is the highest, while
Timer 2 is the lowest.
#ICU 80C186EA 118#
#ICU 80C186XL 118#
#ICU 80C186EB 118#
#ICU 80C186EA 120#
#ICU 80C186XL 120#
#ICU 80C186EB 120#
Check this field to mask (disable) the DMA interrupt, or clear this field to
unmask (enable) the DMA interrupt.
#ICU 80C186EA 119#
#ICU 80C186XL 119#
#ICU 80C186EB 119#
#ICU 80C186EA 121#
#ICU 80C186XL 121#
#ICU 80C186EB 121#
Enter the priority level (0 to 7) for this interrupt.  0 is highest priority
and 7 is lowest priority.
#ICU 80C186EB 125#
#ICU 80C186EB 126#
Check this field to mask (disable) the interrupt, or clear this field to
unmask (enable) the interrupt.
#ICU 80C186EB 127#
Enter the priority level (0 to 7) for this interrupt.  0 is highest priority
and 7 is lowest priority.
#ICU 80C186EB 128#
Check this field to select LEVEL interrupt input triggering, or clear this
field to select EDGE interrupt input triggering.

In level triggering, an interrupt is generated whenever the input is at a high
(1) level.  In edge triggering, an interrupt is generated only when the input
makes a low-to-high transition.
#ICU 80C186EB 136#
Check this field to mask (disable) ALL Serial interrupts, or clear this field
to unmask (enable) Serial interrupts.

NOTE: The two Serial interrupts share a common input request, although each
Serial interrupt has its own vector.  Setting this field masks both Serial
interrupts.  To individually mask Serial interrupts, you must disable them in
the Serial Control Unit.
#ICU 80C186EB 137#
Enter the priority level (0 to 7) for ALL Serial interrupts.  0 is highest
priority and 7 is lowest priority.

NOTE: The two Serial interrupts share a common input request, although each
Serial interrupt has its own vector.  This field sets the priority of ALL
Serial interrupts relative to the other interrupt sources.  Each Serial
interrupt has a fixed priority relative to the other.  Receive is the highest,
while transmit is the lowest.
#ICU 80C186EC 100#
#ICU 80C186EC 108#
Check this field to select LEVEL interrupt input triggering, or clear this
field to select EDGE interrupt input triggering.

In level triggering, an interrupt is generated whenever the input is at a high
(1) level.  In edge triggering, an interrupt is generated only when the input
makes a low-to-high transition.
#ICU 80C186EC 102#
#ICU 80C186EC 110#
Check this field to enable Special Fully Nested Mode, or clear this field to
disable the mode.

Special Fully Nested Mode allows an interrupt from this source to nest within
itself.  Otherwise, the interrupt would be blocked until its in-service bit
has been cleared (by issuing an End-Of-Interrupt).
#ICU 80C186EC 103#
Enter the base vector type that the Slave controller should use.  You may
enter a hex or decimal value, but it must be an integer multiple of 8.  Place
an 'H' at the end of the field entry to designate HEX.

The value of this field is used to generate the vector type for the Slave
Controller.  The vector type is multiplied by 4 (by the CPU) to determine the
interrupt vector address that contains the CS and IP pointers to the interrupt
service routine.

For example, if the value of this field is set to 20H and an interrupt is
generated on IR2, then a vector type of 22H is presented to the CPU during the
acknowledge sequence.  22H is then multiplied by 4 to get the interrupt vector
address.
#ICU 80C186EC 109#
Check this field to select automatic End-of-Interrupt operation, or clear this
field to require specific End-of-Interrupt operation.

In automatic End-of-Interrupt operation, the vector type does not need to be
specified to clear an in-service bit.  However, only the highest priority
interrupt's in-service bit is cleared, which may or may not be the one you
require cleared.

In specific End-of-Interrupt operation, you must specify the vector type of
the in-service bit to be cleared.
#ICU 80C186EC 111#
Enter the base vector type that the Master controller should use.  You may
enter a hex or decimal value, but it must be an integer multiple of 8.  Enter
an 'H' at the end of the field entry to designate HEX.

The value of this field is used to generate the vector type for the Master
Controller.  The vector type is multiplied by 4 (by the CPU) to determine the
interrupt vector address that contains the CS and IP pointer to the interrupt
service routine.

For example, if the value of this field is set to 20H and an interrupt is
generated on IR2, then a vector type of 22H is presented to the CPU during the
acknowledge sequence.  22H is then multiplied by 4 to get the interrupt vector
address.
#ICU 80C186EC 112#
Enter which of the Master interrupt inputs are to be configured for cascade
operation.  You can enter a hex or decimal value, but the value must be 
between 128 (80H) and 255 (0FFH). Place an 'H' at the end of the field entry
to designate HEX.

Each interrupt input is controlled by a bit location in a register.  To
configure the input for cascade operation, you must set the bit location to 1.
The following table can help you determine the appropriate value required to
configure a specific interrupt for cascade mode.  You would OR the values
for each interrupt to configure more than one interrupt input for cascade mode.
#WDT 80C186?? 100#
#WDT 80C186?? 101#
Use this field to enable or disable the watchdog timer.
#WDT 80C186?? 201#
Enter the watchdog timer reload value in this field.
#RCU 80C186?? 30022#
Enter the desired frequency in MHz.
#Serial? 80C186E? 30022#
Enter the clock frequency of either the CPU or the external baud clock
input.

Enter the clock frequency (in megahertz) of the CPU.  For example, if your design
operates at 16 MHz, enter '16' in this field.  If your design operates at 8.3425 MHz,
enter '8.4325'.

Enter the clock frequency (in megahertz) of the external baud clock input.
For example, if your design has the channel's BCLK input operating at 1.8432
MHz, enter '1.8432' in this field.

Remember that the maximum operating frequency of an external baud clock is
1/2 the operating frequency of the CPU.
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