pe186.rd1

mcs51,2051,x86系列MCU

#BIU 80C186E? 226#
#CSU 80C186E? 236#
#BIU 80C186E? 236#
#CSU 80C186E? 246#
#BIU 80C186E? 246#
#CSU 80C186E? 256#
#BIU 80C186E? 256#
#CSU 80C186E? 266#
#BIU 80C186E? 266#
#CSU 80C186E? 276#
#BIU 80C186E? 276#
Check this field to enable bus ready, or clear this field to disable bus
ready.

Clearing this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

Checking this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#PCB 80C186E? 100#
#PCB 80C186XL 100#
Enter the starting (or base) address for the Peripheral Control Block (PCB).
The value you enter can be in hex or in decimal, but it must be an integer
multiple of 256 (100H).  Place an 'H' at the end of the field entry to designate
HEX.

For example, to have the PCB start at 07800H, enter '7800H' in this field.
Entering '512' in this field starts the PCB at 00200H.

When the PCB is mapped to I/O space, the maximum Base Address is 0FF00H.  When
the PCB is mapped to memory space, the maximum Base Address is 0FFF00H.
#PCB 80C186E? 110#
#PCB 80C186XL 110#
Escape (ESC) instruction prefixes are used to extend the math capabilities of
the 80C186 core architecture.  In response to the ESC prefix, the CPU can either
perform a numerics coprocessor operation or perform a software interrupt
(trap) to vector type 16.

By selecting Enable, you are instructing the CPU to perform an ESC TRAP to
vector 16.  Typically this is done to "emulate" the advanced math capabilities
of the numerics coprocessor.
#PCB 80C186E? 111#
#PCB 80C186XL 111#
Escape (ESC) instruction prefixes are used to extend the math capabilities of
the 80C186 core architecture.  In response to the ESC prefix, the CPU can either
perform a numerics coprocessor operation or perform a software interrupt
(trap) to vector type 16.

By selecting Disable, you are instructing the CPU to communicate with an
external numerics coprocessor in response to executing the ESC prefix.
#PCB 80C186E? 115#
#PCB 80C186XL 115#
The Peripheral Control Block (PCB) can be located in either memory address
space or I/O address space.

Selecting I/O means that IN and OUT instructions are used to access the PCB.
I/O address space is limited to 64 Kbytes.
#PCB 80C186E? 116#
#PCB 80C186XL 116#
The Peripheral Control Block (PCB) can be located in either memory address
space or I/O address space.

Selecting Memory means that any of the instructions used to access memory
space can be used to access the PCB.  Memory address space is limited to
1 Mbyte.
#PM 80C186?? 120#
#CPU 80C186?? 120#
#Clock 80C186?? 120#
To reduce current consumption while the CPU is halted, you can selectively
disable the internal clocks.

PowerDown Mode disables all of the internal clocks, including the crystal
oscillator, when the CPU executes a HLT instruction.  Disabling all
clocks reduces current consumption to just microamps.
#PM 80C186?? 121#
#CPU 80C186?? 121#
#Clock 80C186?? 121#
To reduce current consumption while the CPU is halted, you can selectively
disable the internal clocks.

IDLE Mode disables only those clocks used to control the CPU (consisting
of the Execution Unit and the Bus Interface Unit).  This leaves all
peripheral clocks operational.  Disabling only the CPU clocks reduces
current consumption by 30 to 50 percent.
#PM 80C186?? 122#
#CPU 80C186?? 122#
#Clock 80C186?? 122#
To reduce current consumption while the CPU is halted, you can selectively
disable the internal clocks.

When Neither is selected, none of the internal clocks are disabled when the CPU
executes a HLT instruction.  You would do this to disable the PowerDown or
IDLE Mode if either was previously enabled.
#PM 80C186?? 130#
#CPU 80C186?? 130#
#Clock 80C186?? 130#
To reduce current consumption while the CPU is operating, you can selectively
change the internal clock divider to achieve a lower operating frequency.

When Enable is selected, the internal clocks can be reduced in operation by a
programmable Clock Division Factor.  Slowing the clocks in this manner is
similar to changing the input clock by the same factor.

Please note that when Power Save is enabled, all internal peripherals
operate at the new clock rate.  This means that, for instance, the timers will
have a longer timing range than they had at the old clock rate.  You may have
to reprogram the peripherals to adjust to this new clock rate.
#PM 80C186?? 131#
#CPU 80C186?? 131#
#Clock 80C186?? 131#
To reduce current consumption while the CPU is operating, you can selectively
change the internal clock divider to achieve a lower operating frequency.

When Disable is selected, the internal clocks return to their maximum operating
frequency (which is 1/2 the input clock frequency).
#PM 80C186?? 140#
#CPU 80C186?? 140#
#Clock 80C186?? 140#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 1 divisor, which results in the device operating at
its maximum frequency (1/2 the input clock frequency).  Selecting BY 1 is
similar to disabling the Power Save Mode.
#PM 80C186?? 141#
#CPU 80C186?? 141#
#Clock 80C186?? 141#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 4 divisor, which decreases the operating frequency
to 1/4 of maximum (or 1/8 the input clock).
#PM 80C186?? 142#
#CPU 80C186?? 142#
#Clock 80C186?? 142#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 8 divisor, which decreases the operating frequency
to 1/8 of maximum (or 1/16 the input clock).
#PM 80C186?? 143#
#CPU 80C186?? 143#
#Clock 80C186?? 143#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 16 divisor, which decreases the operating frequency
to 1/16 of maximum (or 1/32 the input clock).
#PM 80C186EC 144#
#CPU 80C186EC 144#
#Clock 80C186EC 144#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 32 divisor, which decreases the operating frequency
to 1/32 of maximum (or 1/64 the input clock).
#PM 80C186EC 145#
#CPU 80C186EC 145#
#Clock 80C186EC 145#
When the Power Save Mode is enabled, the Clock Division Factor
defines the desired operating frequency.

You have selected the BY 64 divisor, which decreases the operating frequency
to 1/64 of maximum (or 1/128th the input clock).
#RCU 80C186?? 100#
Enter the starting (base) address to be used for refresh bus operations.  The
value you enter can be in hex or decimal, but it must be an integer multiple of
4096 (1000H).  Place an 'H' at the end of the field entry to designate HEX.

For example, to have the refresh base address start at 80000H, enter '80000H'
in this field.  Entering 32768 in this field sets the base address at 08000H.
#RCU 80C186?? 110#
Selecting this option enables the Refresh Control Unit.
#RCU 80C186?? 111#
Selecting this option disables the Refresh Control Unit.
#RCU 80C186?? 120#
Enter the time (in microseconds) that you wish to delay between successive
refresh cycles.  This time is usually calculated by dividing the refresh
period by the number of refresh rows. (Both values are specified by the dynamic
memory manufacturer).

For example, a 4-Mbit memory device has a refresh period of 8ms and 512
refresh rows.  Dividing 8ms by 512 results in 15.5 us.  '15.5' would be
entered to provide the proper refresh rate for a 4-Mbit memory device.
#RCU 80C186?? 140#
Enter the operating frequency (in megahertz) of the CPU.  For example, if your
application operates at 16 MHz, enter '16' in this field.
#Timer? 80C186?? 110#
Check this field to enable the timer, or clear this field to disable the
timer.

NOTE: If you really want to enable or disable the timer, you must also CLEAR
the Inhibit field.  The Inhibit field is used to prevent the timer
enable/disable control bit from being modified when writing to the timer
control register.
#Timer? 80C186?? 111#
Check this field to prevent the timer enable/disable control bit from being
modified, or clear this field to allow the control bit to be modified.

It is sometimes necessary to modify other operating characteristics of the
timer without changing the enabled/disabled state.  This field allows you to
do that.
#Timer0 80C186?? 112#
#Timer1 80C186?? 112#
Check this field to enable interrupts when a timer compare occurs, or clear
this field to prevent a timer interrupt.

When you enable this field, an interrupt is generated every time a timer
compare occurs (for both maximum counts, if the Alternate Compare Register
field is checked).
#Timer2 80C186?? 112#
Check this field to enable interrupts when a timer compare occurs, or clear
this field to prevent a timer interrupt.

When you enable this field, an interrupt is generated every time a timer
compare occurs.
#Timer0 80C186?? 113#
#Timer1 80C186?? 113#
Check this field to retrigger the timer on a low-to-high transition on the
timer input pin.  Clear this field to disable retriggering.  Retriggering the
timer clears its Count register.

NOTE: This field is effective only if the timer is internally clocked.
External clocking prevents the timer input pin from being used as a
retrigger input.

The retrigger function is useful for implementing digital one-shots or for
setting the Count register to zero at a known time.
#Timer? 80C186?? 114#
Check this field to use the output of Timer 2 as the clock input to the timer,
or clear this field to use a fixed internal clock as the timer clock input.

NOTE: This field is effective only if the timer is internally clocked.
External clocking defeats the purpose of using this field.

Using Timer 2 as a clock enables the timer to count at long intervals.  The
fixed internal clock operates at 1/4 the CPU operating frequency.
#Timer? 80C186?? 115#
Check this field to use the timer抯 input pin as the source of the timer
clock, or clear this field to clock the timer internally by Timer 2 or a fixed
clock source.
#Timer? 80C186?? 116#
Check this field to enable continuous timer operation, or clear this field to
stop timer operation after a timing cycle has completed.

A timing cycle is completed when the timer counter reaches the value of
maximum count register A (in single count mode) or maximum count 
register B (in dual count mode, Timers 0 and 1 only).
#Timer? 80C186?? 118#
Check this field to select dual compare mode, or clear this field to select
single compare mode.

In single compare mode, a timing cycle has completed when the count register
reaches maximum count register A.  In dual compare mode, a timing cycle has
completed after the count register reaches maximum count register A, resets to
zero, and then reaches maximum count register B.

In dual compare mode, the timer's output pin is high while a compare to maximum
count register A is being checked, and is low while a compare to maximum count
register B is being checked.  In single compare mode, the timer's output pin
toggles low for one clock when the count register reaches the value in maximum
count register A.
#Timer0 80C186?? 120#
#Timer1 80C186?? 120#
Enter the value you wish to have as the maxcount compare value.  You can enter
the value in hex or in decimal, but you cannot exceed 65,535 (0FFFFH).  Place
an 'H' at the end of the field entry to designate HEX.
#Timer0 80C186?? 121#
#Timer1 80C186?? 121#
Enter the value you wish to have as the maxcount compare value.  You can enter
the value in hex or in decimal, but you cannot exceed 65,535 (0FFFFH).  Place
an 'H' at the end of the field entry to designate HEX.
#Timer2 80C186?? 130#
Enter the value you wish to have as the maxcount compare value.  You can enter
the value in hex or in decimal, but you cannot exceed 65,535 (0FFFFH).  Place
an 'H' at the end of the field entry to designate HEX.
#DMA? 80C186?? 101#
Enter the starting address location that points to the source of the DMA data
transfer.  You can enter the value in hex or in decimal.  Place an 'H' at the
end of the field entry to designate HEX.

This field should not exceed 0FFFFH when DMA transfers occur in I/O space.
Remember that I/O space is only 64 Kbytes in size, and anything above 64K is
not directly reachable by the CPU.
#DMA? 80C186?? 102#
Enter the starting address location that points to the destination of the DMA
data transfer.  You can enter the value in hex or in decimal.  Place an 'H'
at the end of the field entry to designate HEX.

This field should not exceed 0FFFFH when DMA transfers occur in I/O space.
Remember that I/O space is only 64 Kbytes in size, and anything above 64K is
not directly reachable by the CPU.
#DMA? 80C186?? 103#
Enter the number of DMA transfers you would like to complete before halting
any further transfers.  You can enter the value in hex or in decimal.  Place
an 'H' at the end of the field entry to designate HEX.

This field cannot exceed 0FFFFH (or 65,535).  A value of 0 is used to halt
after 65,536 transfers.
#DMA? 80C186?? 104#
Selecting Unsynchronized automatically starts a DMA transfer when the
channel is enabled.  While in this mode, DMA transfers continue until
the count register decrements to zero, and then the channel is disabled.
Use this mode when DMA transfers are to be initiated in software
(no external DRQ signal is required).
#DMA? 80C186?? 105#
Selecting Source requires that a DRQ be generated to start a DMA
transfer, and that it be removed at least four clocks before the end of 
the deposit cycle to prevent another DMA transfer from occurring.

Use this mode when the DMA request comes from the SOURCE of the data transfer.
When the DMA transfer occurs, the DMA request can be removed during the fetch
cycle to prevent another DMA transfer from occurring.
#DMA? 80C186?? 106#
Selecting Destination provides at least two bus idle states between the completion
of one DMA transfer and the start of another.  However, unless the CPU has been
 halted, the two bus idle states are often replaced with a CPU bus cycle
(e.g., instruction fetch).

Use this mode when the DMA request comes from the DESTINATION of the data
transfer and the DRQ signal cannot be removed in time to prevent a false DMA
request.
#DMA? 80C186?? 107#
Check this field to indicate that the source address applies to memory address
space, or clear this field to indicate that the source address applies to I/O
address space.
#DMA? 80C186?? 108#
Check this field to increment the source address after a DMA transfer
completes, or clear this field to prevent the source address from being
incremented after a DMA transfer completes.

NOTE: To correctly specify that the source address increment after a completed
transfer, you must set this field and clear the Decrement field.  When both