pe186.rd1

mcs51,2051,x86系列MCU

receiver listening to a dead line or when you are simply not interested in
enabling the receiver.
#Serial? 80C186E? 109#
Check this field to select even parity generation/checking, or clear this
field to select odd parity generation/checking.

The value of this field has an effect only when parity has been enabled.
#Serial? 80C186E? 110#
Check this field to enable parity generation/checking, or clear this field to
disable parity generation/checking.  Parity is not available when the Serial
Channel is configured for Mode 0 or Mode 4.
#Serial? 80C186E? 120#
#Serial? 80C186E? 121#
Determine the Baud Rate clocking source.

When "Internal" is selected, the CPU becomes the input to the baud clock.  When
"External" is selected, the BCLK becomes the input to the baud clock.
#CSU 80C186EA 100#
#BIU 80C186EA 100#
#CSU 80C186XL 100#
#BIU 80C186XL 100#
Select which start address/block size configuration you would like to apply to
the Upper Memory Chip-Select pin (UCS#).  Only those options shown are
available.
#CSU 80C186EA 101#
#BIU 80C186EA 101#
#CSU 80C186XL 101#
#BIU 80C186XL 101#
Enter the number of wait states to be automatically inserted into a bus cycle
whose address is within that defined for UCS#.  You can enter a number between
0 and 3.
#CSU 80C186EA 102#
#BIU 80C186EA 102#
#CSU 80C186XL 102#
#BIU 80C186XL 102#
Check this field to disable bus ready, or clear this field to require bus
ready to complete a bus cycle whose address is within that defined for UCS#.

Checking this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

Clearing this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#CSU 80C186EA 103#
#CSU 80C186XL 103#
#BIU 80C186EA 103#
#BIU 80C186XL 103#
Select which end address/block size configuration you would like to apply to
the Lower Memory Chip-Select pin (LCS#).  Only those options shown are
available.
#CSU 80C186EA 104#
#CSU 80C186XL 104#
#BIU 80C186EA 104#
#BIU 80C186XL 104#
Enter the number of wait states required to be automatically inserted into a
bus cycle whose address is within that defined for LCS#.  You can enter a
number between 0 and 3.
#CSU 80C186EA 105#
#CSU 80C186XL 105#
#BIU 80C186EA 105#
#BIU 80C186XL 105#
Check this field to disable bus ready, or clear this field to require bus
ready to complete a bus cycle whose address is within that defined for LCS#.

Checking this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

Clearing this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#CSU 80C186EA 106#
#CSU 80C186XL 106#
#BIU 80C186EA 106#
#BIU 80C186XL 106#
Enter the starting address for the Midrange Chip-Select (MCS) pins.  The value
can be in hex or in decimal, but it must be an integer multiple of the MCS block
size.  Place an 'H' at the end of the field entry to designate HEX.
#CSU 80C186EA 107#
#CSU 80C186XL 107#
#BIU 80C186EA 107#
#BIU 80C186XL 107#
Select the block size configuration you would like to apply to the Midrange
Chip-Select (MCS) pins.  Only those options shown are available.
#CSU 80C186EA 108#
#CSU 80C186XL 108#
#BIU 80C186EA 108#
#BIU 80C186XL 108#
Enter the number of wait states required to be automatically inserted into a
bus cycle whose address is within that defined for all MCS# pins.  You can
enter a number between 0 and 3.
#CSU 80C186EA 109#
#CSU 80C186XL 109#
#BIU 80C186EA 109#
#BIU 80C186XL 109#
Check this field to disable bus ready, or clear this field to require bus
ready to complete a bus cycle whose address is within that defined for all
MCS# pins.

Checking this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

 
Clearing this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#CSU 80C186EA 110#
#CSU 80C186XL 110#
#BIU 80C186EA 110#
#BIU 80C186XL 110#
Enter the starting address for the Peripheral Chip-Select (PCS#) pins.  You
can enter the value in hex or in decimal, but the value must be an integer
multiple of 1024 (400H).  Place an 'H' at the end of the field entry to designate
HEX.
#CSU 80C186EA 111#
#CSU 80C186XL 111#
#BIU 80C186EA 111#
#BIU 80C186XL 111#
Enter the number of wait states required to be automatically inserted into a
bus cycle whose address is within that defined for the lower four PCS# pins.
You can enter a number between 0 and 3.
#CSU 80C186EA 112#
#CSU 80C186XL 112#
#BIU 80C186EA 112#
#BIU 80C186XL 112#
Check this field to disable bus ready, or clear this field to require bus
ready to complete a bus cycle whose address is within that defined for the
lower four PCS# pins.

Checking this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

Clearing this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#CSU 80C186EA 113#
#CSU 80C186XL 113#
#BIU 80C186EA 113#
#BIU 80C186XL 113#
Check this field to keep PCS5# and PCS6# as chip-selects, or clear this field to
reconfigure PCS5# as latched address bit 1 (LA1) and PCS6# as latched address
bit 2 (LA2).
#CSU 80C186EA 114#
#CSU 80C186XL 114#
#BIU 80C186EA 114#
#BIU 80C186XL 114#
Check this field to place the Peripheral Chip-Selects in I/O address space, or
clear this field to place the Peripheral Chip-Selects in memory address
space.
#CSU 80C186EA 115#
#CSU 80C186XL 115#
#BIU 80C186EA 115#
#BIU 80C186XL 115#
Enter the number of wait states required to be automatically inserted into a
bus cycle whose address is within that defined for the upper three PCS# pins.
You can enter a number between 0 and 3.
#CSU 80C186EA 116#
#CSU 80C186XL 116#
#BIU 80C186EA 116#
#BIU 80C186XL 116#
Check this field to disable bus ready, or clear this field to require bus
ready to complete a bus cycle whose address is within that defined for the
upper three PCS# pins.

Checking this field means that a bus ready is not required to complete a bus
cycle.  The bus cycle will execute wait states only if they have been
programmed in the Wait States field.

Clearing this field means that bus ready is required to complete a bus cycle.
This allows the bus cycle to extend the number of wait states beyond the
number programmed into the Wait States field.
#CSU 80C186E? 180#
#BIU 80C186E? 180#
#CSU 80C186E? 190#
#BIU 80C186E? 190#
#CSU 80C186E? 200#
#BIU 80C186E? 200#
#CSU 80C186E? 210#
#BIU 80C186E? 210#
#CSU 80C186E? 220#
#BIU 80C186E? 220#
#CSU 80C186E? 230#
#BIU 80C186E? 230#
#CSU 80C186E? 240#
#BIU 80C186E? 240#
#CSU 80C186E? 250#
#BIU 80C186E? 250#
#CSU 80C186E? 260#
#BIU 80C186E? 260#
#CSU 80C186E? 270#
#BIU 80C186E? 270#
Enter the starting address for the chip-select.  You can enter a hex or
decimal value.  Place an 'H' at the end of the field entry to designate HEX.

This field has some limitations that you must be aware of.  You can start only
on integer multiples of 1024 (400H) for memory-mapped operation and
on integer multiples of 64 (40H) for I/O-mapped operation.
#CSU 80C186E? 181#
#BIU 80C186E? 181#
#CSU 80C186E? 191#
#BIU 80C186E? 191#
#CSU 80C186E? 201#
#BIU 80C186E? 201#
#CSU 80C186E? 211#
#BIU 80C186E? 211#
#CSU 80C186E? 221#
#BIU 80C186E? 221#
#CSU 80C186E? 231#
#BIU 80C186E? 231#
#CSU 80C186E? 241#
#BIU 80C186E? 241#
#CSU 80C186E? 251#
#BIU 80C186E? 251#
#CSU 80C186E? 261#
#BIU 80C186E? 261#
#CSU 80C186E? 271#
#BIU 80C186E? 271#
Enter the ending address for the chip-select.  You can enter a hex or decimal
value.  Place an 'H' at the end of the field entry to designate HEX.

This field has some limitations that you must be aware of.  You can end only
on integer multiples of 1024 (400H) for memory-mapped operation and
on integer multiples of 64 (40H) for I/O-mapped operation.  To end at the top
of memory (or I/O) space, you must check the Ignore Stop Address field.
#CSU 80C186E? 182#
#BIU 80C186E? 182#
#CSU 80C186E? 192#
#BIU 80C186E? 192#
#CSU 80C186E? 202#
#BIU 80C186E? 202#
#CSU 80C186E? 212#
#BIU 80C186E? 212#
#CSU 80C186E? 222#
#BIU 80C186E? 222#
#CSU 80C186E? 232#
#BIU 80C186E? 232#
#CSU 80C186E? 242#
#BIU 80C186E? 242#
#CSU 80C186E? 252#
#BIU 80C186E? 252#
#CSU 80C186E? 262#
#BIU 80C186E? 262#
#CSU 80C186E? 272#
#BIU 80C186E? 272#
Enter the number of wait states required to be automatically inserted into a
bus cycle whose address is within that defined for the chip-select.  You can
enter a number between 0 and 15 (decimal) or 0H and 0FH (hex).
#CSU 80C186E? 183#
#BIU 80C186E? 183#
#CSU 80C186E? 193#
#BIU 80C186E? 193#
#CSU 80C186E? 203#
#BIU 80C186E? 203#
#CSU 80C186E? 213#
#BIU 80C186E? 213#
#CSU 80C186E? 223#
#BIU 80C186E? 223#
#CSU 80C186E? 233#
#BIU 80C186E? 233#
#CSU 80C186E? 243#
#BIU 80C186E? 243#
#CSU 80C186E? 253#
#BIU 80C186E? 253#
#CSU 80C186E? 263#
#BIU 80C186E? 263#
#CSU 80C186E? 273#
#BIU 80C186E? 273#
Check this field to enable the chip-select, or clear this field to disable the
Chip-Select.

NOTE: An enabled chip-select will go active only if its stop address is
greater than its start address.
#CSU 80C186E? 184#
#BIU 80C186E? 184#
#CSU 80C186E? 194#
#BIU 80C186E? 194#
#CSU 80C186E? 204#
#BIU 80C186E? 204#
#CSU 80C186E? 214#
#BIU 80C186E? 214#
#CSU 80C186E? 224#
#BIU 80C186E? 224#
#CSU 80C186E? 234#
#BIU 80C186E? 234#
#CSU 80C186E? 244#
#BIU 80C186E? 244#
#CSU 80C186E? 254#
#BIU 80C186E? 254#
#CSU 80C186E? 264#
#BIU 80C186E? 264#
#CSU 80C186E? 274#
#BIU 80C186E? 274#
Check this field to disable stop address field checking, or clear this field
to enable stop address field checking.

You must check this field to allow a chip-select to be active to the end of
the memory or I/O address space.  Otherwise, the chip-select is active only
until it reaches the 1 Kbyte (memory) or 64 byte (I/O) address block below the
ending address.
#CSU 80C186E? 185#
#BIU 80C186E? 185#
#CSU 80C186E? 195#
#BIU 80C186E? 195#
#CSU 80C186E? 205#
#BIU 80C186E? 205#
#CSU 80C186E? 215#
#BIU 80C186E? 215#
#CSU 80C186E? 225#
#BIU 80C186E? 225#
#CSU 80C186E? 235#
#BIU 80C186E? 235#
#CSU 80C186E? 245#
#BIU 80C186E? 245#
#CSU 80C186E? 255#
#BIU 80C186E? 255#
#CSU 80C186E? 265#
#BIU 80C186E? 265#
#CSU 80C186E? 275#
#BIU 80C186E? 275#
Check this field to configure the chip-select active for memory address space,
or clear this field to configure the chip-select active for I/O address
space.
#CSU 80C186E? 186#
#BIU 80C186E? 186#
#CSU 80C186E? 196#
#BIU 80C186E? 196#
#CSU 80C186E? 206#
#BIU 80C186E? 206#
#CSU 80C186E? 216#
#BIU 80C186E? 216#
#CSU 80C186E? 226#