51fxa.cod

mcs51,2051,x86系列MCU

/*
 *  Copyright (c) 1995, Intel Corporation
 *
 *  $Workfile:   51fxa.cod  $
 *  $Revision:   1.5  $
 *  $Modtime:   May 29 1995 12:50:24  $
 *
 *  Purpose:
 *
 *
 *
 *
 *
 *  Compiler:       
 *
 *  Ext Packages:   
 *
 * 
 *
 */
##80C5? WRITE#
##80C51F? WRITE#
mov     @@REG_MNEM@, #$%aREG_VALUE$
##80C5? READ#
##80C51F? READ#
mov     UserVar, @@REG_MNEM@
##80C5? OR#
##80C51F? OR#
orl     @@REG_MNEM@, #$%aREG_VALUE$
##80C5? AND#
##80C51F? AND#
anl     @@REG_MNEM@, #$%aREG_VALUE$
##80C5? XOR#
##80C51F? XOR#
xrl     @@REG_MNEM@, #$%aREG_VALUE$
##80C5? TESTZ#
##80C51F? TESTZ#
mov     A, @@REG_MNEM@
jz
##80C5? TESTNZ#
##80C51F? TESTNZ#
mov     A, @@REG_MNEM@
jnz
##80C52 IU#
##80C54 IU#
##80C58 IU#
##80C51FA IU#
##80C51FB IU#
##80C51FC IU#
include "51fx.inc"

; Interrupt Control Unit


$$ifn$IE
;    NO INTERRUPTS
$$end$
$$if$IE
;   ****  Enabled interrupts in Interrupt Enable Register ****

;    ****  GLOBAL INTERRUPT MUST BE ENABLED FOR ANY OTHER
;    ****  INTERRUPT TO WORK!                                

      $$if$IE.7
;                  GLOBAL INTERRUPT ENABLED
     $$end$
      $$ifN$IE.7
;                  GLOBAL INTERRUPT DISABLED ALL INTERRUPTS
;                              ARE DISABLED
     $$end$

$$if$IE.0
;                  External interrupt 0
                    $$ifn$IPH.0 &! IP.0
;                        Priority Level = 0
                    $$end$
                $$ifn$IPH.0 && IP.0
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.0 &! IP.0
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.0 && IP.0
;                        Priority Level = 3
                    $$end$

     $$end$
      $$if$IE.1
;                  Timer 0 interrupt
               $$ifn$IPH.1 &! IP.1
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.1 && IP.1
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.1 &! IP.1
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.1 && IP.1
;                        Priority Level = 3
                    $$end$

     $$end$
      $$if$IE.2
;                  External interrupt 1
                       $$ifn$IPH.2 &! IP.2
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.2 && IP.2
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.2 &! IP.2
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.2 && IP.2
;                        Priority Level = 3
                    $$end$

     $$end$
      $$if$IE.3
;                  Timer 1 interrupt
                       $$ifn$IPH.3 &! IP.3
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.3 && IP.3
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.3 &! IP.3
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.3 && IP.3
;                        Priority Level = 3
                    $$end$

     $$end$

      $$if$IE.4
;                  Serial Port interrupt
                       $$ifn$IPH.4 &! IP.4
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.4 && IP.4
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.4 &! IP.4
;                      Priority Level = 2
                    $$end$
                    $$if$IPH.4 && IP.4
;                        Priority Level = 3
                    $$end$

     $$end$
      $$if$IE.5
;                  Timer 2 interrupt
                       $$ifn$IPH.5 &! IP.5
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.5 && IP.5
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.5 &! IP.5
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.5 && IP.5
;                        Priority Level = 3
                    $$end$

     $$end$
      $$if$IE.6
;                  PCA interrupt
                       $$ifn$IPH.6 &! IP.6
;                        Priority Level = 0
                    $$end$
                    $$ifn$IPH.6 && IP.6
;                        Priority Level = 1
                    $$end$
                    $$if$IPH.6 &! IP.6
;                        Priority Level = 2
                    $$end$
                    $$if$IPH.6 && IP.6
;                        Priority Level = 3
                    $$end$

     $$end$

$$end$
init_special_interrupts:

      mov   IE, #0$$IE$h
      mov   IP, #0$$IP$h
      mov   IPH, #0$$IPH$h

      ret


main:
      lcall init_special_interrupts
end

##80C51F? PCATMR#
include "51fx.inc"

; PCA Timer/Counter
;    Clocking Source:  $%4CMOD.1-2$Fosc/12$Fosc/4$Timer 0 Overflow$External input (ECI)$
;    Run Control:  PCA Timer is $%eCCON.2$
$$if$ CCON.6
$$if$ CMOD.7
;                  (halts during idle mode)
$$end$
$$end$
;    Timer Count: $$CH$$$CL.4-7$$$CL.0-3$H
$$if$ IE.6
;    PCA global interrupt:  enabled
$$if$ CMOD.0
;         --Enable PCA overflow interrupt
$$end$
$$if$ (IE.7 == 0)
;         NOTE:  The global disable bit is clear;
;                all interrupts are disabled.
$$end$
$$end$

init_pca_tmr:

   clr CR                        ; Turn off PCA timer to load count
   mov CL, #0$$CL$H                 ; Set PCA count (low byte)
   mov CH, #0$$CH$H                 ; Set PCA count (high byte)

$$if$ IE.6
   setb EC                       ; Enable PCA global interrupt
$$end$
$$else$
   clr EC                        ; Disable PCA global interrupt
$$end$
$$if$ CMOD.0
   orl CMOD, #01H                ; Enable PCA overflow interrupt
$$end$
$$else$
   anl CMOD, #0FEH               ; Disable PCA overflow interrupt
$$end$
   anl CMOD, #0F9H               ; Set clocking input source
   orl CMOD, #$%4CMOD.1-2$00$02$04$06$H
$$if$ CMOD.7
	orl CMOD, #80H                ; Set counter idle control
$$end$
$$else$
   anl CMOD, #7FH                ; Clr counter idle control
$$end$

$$if$ CCON.6
   setb CR                       ; Enable PCA Timer/Counter
$$end$
   ret

main:
   lcall init_pca_tmr
end


##80C51F? PCAMODULE#
include "51fx.inc"

;  PCA module $$PCAMODULE$
$$if$ (PCATYPE == 0)
;     Disabled
$$end$
$$if$ (PCATYPE == 1)
;     Capture Mode:  trigger on a positive transition
$$end$
$$if$ (PCATYPE == 2)
;     Capture Mode:  trigger on a negative transition
$$end$
$$if$ (PCATYPE == 3)
;     Capture Mode:  trigger on a positive or negative transition
$$end$
$$if$ (PCATYPE == 4)
;     Compare Mode:  software timer
$$end$
$$if$ (PCATYPE == 5)
;     Compare Mode:  high-speed output
$$end$
$$if$ (PCATYPE == 6)
;     Compare Mode:  pulse width modulation
$$end$
$$if$ (PCATYPE == 7)
;     Compare Mode:  watchdog timer
$$end$
$$if$ (PCATYPE == 1) || (PCATYPE == 2) || (PCATYPE == 3)
$$if$ CCAPMx.0
;     Interrupts:  PCA capture enabled
$$ifn$ IE.6
;           NOTE:  The PCA global interrupt is disabled
$$end$
$$end$
$$end$
$$if$ (PCATYPE == 4) || (PCATYPE == 5) || (PCATYPE == 7)
$$if$ CCAPMx.0
;     Interrupts:  PCA compare is enabled
$$ifn$ IE.6
;           NOTE:  The PCA global interrupt is disabled
$$end$
$$end$
$$end$

init_pca_module$$PCAMODULE$:
$$if$ (PCATYPE == 7)
   anl CMOD, #0BFH             ; Disable watchdog mode to load compare values
$$end$
   mov CCAPM$$PCAMODULE$, #0$$CCAPMx$H
$$if$ (PCATYPE == 4) || (PCATYPE == 5) || (PCATYPE == 7)
   mov CCAP$$PCAMODULE$L, #0$$CCAPxL$H
   mov CCAP$$PCAMODULE$H, #0$$CCAPxH$H
$$end$
$$if$ (PCATYPE == 6)
                              ;To change the value in CCAP$$PCAMODULE$L w/o
                              ;   glitches write new value into CCAP$$PCAMODULE$H
   mov CCAP$$PCAMODULE$H, #0$$CCAPxL$H
$$end$
$$if$ (PCATYPE == 7)

   orl CMOD, #40H             ; Enable watchdog mode
$$end$
   ret

main:
     lcall init_pca_module$$PCAMODULE$
end

##80C52 IO_P0#
##80C54 IO_P0#
##80C58 IO_P0#
##80C51FA IO_P0#
##80C51FB IO_P0#
##80C51FC IO_P0#

include "51fx.inc"

; Initialize the quasi-bidirectional port pins.  To use these
; pins as inputs they must be written with a one.


; IO port pins: