hl251.txt

mcs51,2051,x86系列MCU

#PCA 80C251SA#
#PCA 80C251SB#
#PCA 80C251SP#
#PCA 80C251SQ#
Programmable Counter Array\n
 - Measures periods, pulse widths, duty cycles, and phase differences\n
 - 16-bit timer/counter with 250-ns resolution at 16 MHz\n
 - Five high-speed, 16-bit modules\n
     Input capture: rising, falling, or both edges\n
     Output compare\n
     Pulse-width modulation\n
     Programmable 16-bit watchdog timer (module 4 only)\n
#Serial 80C251SA#
#Serial 80C251SB#
#Serial 80C251SP#
#Serial 80C251SQ#
Serial Port\n
 - Full duplex\n
 - One synchronous and three asynchronous modes\n
 - Variable baud rate\n
 - Framing error detection\n
 - Multi-processor communications\n
 - Automatic address recognition\n
 - Interrupt on reception and transmission of data byte\n
#Clock 80C251SA#
Clock\n
 - 8X251SA16 operates at 0 - 16 MHz\n
#Clock 80C251SB#
Clock\n
 - 8X251SB16 operates at 0 - 16 MHz\n
#Clock 80C251SP#
Clock\n
 - 8X251SP16 operates at 0 - 16 MHz\n
#Clock 80C251SQ#
Clock\n
 - 8X251SQ16 operates at 0 - 16 MHz\n
#Timer 80C251SA#
#Timer 80C251SB#
#Timer 80C251SP#
#Timer 80C251SQ#
Timer/Counters\n
 - Three 16-bit units: timer 0, timer 1, timer 2\n
 - Timer or counter operation\n
 - Internal or external clocking\n
\n
 - Timer 0 and timer 1 modes:\n
     13-bit timer or counter\n
     16-bit timer or counter\n
     8-bit auto-reload timer or counter\n
     Two 8-bit timers\n 
\n
 - Timer 2 modes:\n 
     Auto-reload (up or up/down counter/timer)\n
     Independent event capture\n
     Baud rate generator\n
     Programmable clock-out at 50% duty cycle\n 
#CPU 80C251SA#
#CPU 80C251SB#
#CPU 80C251SP#
#CPU 80C251SQ#
Central Processing Unit\n
 - High-performance CPU\n
 - Binary- and source-mode compatible with MCS 51 microcontrollers\n
 - Linear address space\n
 - Register-based architecture\n
 - Enriched instruction set\n 
     8-, 16-, and 32-bit data-transfer instructions\n
     8-, 16-, and 32-bit arithmetic instructions\n
     8-, 16-, and 32-bit control instructions\n
     Supports two-operand instructions\n
 - Pipeline CPU\n
 - Two bytes/state code fetch (internal execution)\n
 - Two bytes/state data fetch (internal execution)\n
#WDT 80C251SA#
#WDT 80C251SB#
#WDT 80C251SP#
#WDT 80C251SQ#
Watchdog Timer\n
 - 14-bit timer\n
 - Allows recovery from system upsets\n
 - Increases system reliability\n
 - One-time enabled\n 
 - Resets chip on overflow\n
#DATA 80C251SA#
#DATA 80C251SB#
RAM\n
 - 1024-byte on-chip general-purpose data RAM,\n
    accessible by direct addressing\n
 - Up to 256 Kbytes of external data memory\n
#DATA 80C251SP#
#DATA 80C251SQ#
RAM\n
 - 512-byte on-chip general-purpose data RAM,\n
    accessible by direct addressing\n
 - Up to 256 Kbytes of external data memory\n
#CODE 80C251SA#
EPROM/OTPROM/ROM\n
 - 8-Kbyte on-chip program memory\n
 - Up to 256 Kbytes of external program memory\n
#CODE 80C251SB#
EPROM/OTPROM/ROM\n
 - 16-Kbyte on-chip program memory\n
 - Up to 256 Kbytes of external program memory\n
#CODE 80C251SP#
EPROM/OTPROM/ROM\n
 - 8-Kbyte on-chip program memory\n
 - Up to 256 Kbytes of external program memory\n
#CODE 80C251SQ#
EPROM/OTPROM/ROM\n
 - 16-Kbyte on-chip program memory\n
 - Up to 256 Kbytes of external program memory\n
#IO 80C251SA# 
#IO 80C251SB# 
#IO 80C251SP# 
#IO 80C251SQ# 
I/O Ports\n
 - 32 bidirectional I/O pins\n
#BU 80C251SA#
#BU 80C251SB#
#BU 80C251SP#
#BU 80C251SQ#
Bus Interface Unit\n
 - 16-Mbyte addressability (24-bit internal address bus)\n
#IU 80C251SA#
#IU 80C251SB#
#IU 80C251SP#
#IU 80C251SQ#
Interrupt Control Unit\n
 - Seven interrupt sources\n
 - Four priority levels\n
#PM 80C251SA#
#PM 80C251SB#
#PM 80C251SP#
#PM 80C251SQ#
Power Management\n
 Idle mode\n
    - SFRs and on-chip data RAM retain their values\n
    - Peripherals continue to operate\n
    - Any enabled interrupt awakens the chip\n
\n
Powerdown mode\n
    - SFRs and on-chip data RAM retain their values\n
    - Peripherals stop operation\n
    - Any enabled external interrupt awakens the chip\n
    - Vcc can be reduced as low as 2 V\n
\n
 Power off flag\n
    - Used to distinguish between\n
      'cold-start' reset and 'warm-start' reset\n
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