386exa.cod

mcs51,2051,x86系列MCU

;  $%2SIOCFG.7$External$Internal$ modem control sources.
;  @@SIO1BAUDRATE@(@@SIO1BAUDERROR@%) bps baud rate.
;  Interrupt sources:
$$IFN$IER1.0-3
;                None Enabled
$$END$
$$IF$IER1.0
;                Reception Complete Interrupt
$$END$
$$IF$IER1.1
;                Transmission Register Empty Interrupt
$$END$
$$IF$IER1.2
;                Receive Line Status Interrupt
$$END$
$$IF$IER1.3
;                Modem Status Interrupt
$$END$

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_SIO1 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX
 

$$END$
  _SetEXRegByte SIOCFG, 0$$SIOCFG$H    ;Set clocking and modem control sources.
  _SetEXRegByte LCR1$%2REMAPCFG.6$DOS$$, 080H     ;Access divisor latch.
  _SetEXRegByte DLH1$%2REMAPCFG.6$DOS$$, 0$$DLH1$H      ;Set the divisor for the baud rate generator.
  _SetEXRegByte DLL1$%2REMAPCFG.6$DOS$$, 0$$DLL1$H
  _SetEXRegByte LCR1$%2REMAPCFG.6$DOS$$, 0$$LCR1$H      ;Set parity, stop bits, and word size.
  _SetEXRegByte IER1$%2REMAPCFG.6$DOS$$, 0$$IER1$H      ;Enable selected interrupts.

  MOV DX, IIR1$%2REMAPCFG.5$DOS$$                 ;Clear all interrupts at start.
  IN  AL, DX

  _SetEXRegByte P3CFG, 0$$P3CFG$H   ;Set P3CFG and PINCFG registers to set signal paths.
  _SetEXRegByte PINCFG, 0$$PINCFG$H
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
  _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_SIO1 ENDP

_TEXT ENDS
END

##80C386EX CPU#
;Initialize  CPU Addressing for:
;  Addressing mode is: $%4CPUOPMODE.0-1$DOS compatible$non-intrusive DOS$enhanced DOS$non-DOS$ mode.

$$IFN$REMAPCFG
;  Only slot 0 peripherals are accessible in this mode.
$$END$
$$IF$REMAPCFG
;  Peripherals is slots 0 and 15 are accessible, however
;    all 16 address lined must be decoded.
$$END$

;  Serial channel 0 is in ==> $%2REMAPCFG.5$slot 0$slot 15$.
;  Serial channel 1 is in ==> $%2REMAPCFG.6$slot 0$slot 15$.
;  Slave 8259A is in =======> $%2REMAPCFG.4$slot 0$slot 15$.
;  Master 8259A is in ======> $%2REMAPCFG.3$slot 0$slot 15$.
;  DMA's are in ============> $%2REMAPCFG.2$slot 0$slot 15$.
;  Timer's are in ==========> $%2REMAPCFG.0$slot 0$slot 15$.

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_CPUAddressing Proc Far
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX

  _SetEXRegByte REMAPCFGL, 0$$REMAPCFG.0-7$H  ;Map peripherals
$$IFN$REMAPCFG.15
  _SetEXRegByte REMAPCFGH, 0$$REMAPCFG.8-15$H  ;Disable expanded I/O space
$$END$

RET
Init_CPUAddressing ENDP

_TEXT ENDS
END

##80C386EX RCU#
;Initialize the Refresh Control Unit for:
;  Refresh address of @@REF_ADDRESS@000H.
;  Refresh gate between rows is @@REF_TIME@uSec.
;  Using a CPU frequency of @@CPU_FREQ@.
;  The refresh control unit is $%ERFSCON.15$.
;  The external pin is connected to $%2PINCFG.6$CS6#$REFRESH#$.
;
INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_RCU Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX
 

$$END$
  _SetEXRegByte PINCFG, 0$$PINCFG$H         ;Program external pin function.
  _SetEXRegWord RFSCIR, 0$$RFSCIR$H         ;Program refresh interval.
  _SetEXRegWord RFSBAD, 0$$RFSBAD$H         ;Program base address.
  _SetEXRegWord RFSADD, 0$$RFSADD$H         ;Program address register.
  _SetEXRegWord RFSCON, 0$$RFSCON$H         ;Program the enable bit.
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
  _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_RCU ENDP

_TEXT ENDS
END
##80C386EX WDT#
;Initialize the Watch Dog Timer for:
;  Watch Dog Timer Status = $%4WDT_OP_MODE.0-1$Enabled$Disabled$General Purpose Timer$Bus Monitor Mode$.
$$IFN$WDT_OP_MODE.0 || WDT_OP_MODE.1
;  WDT Reload Value = 0$$WDTRLDH$:$$WDTRLDL$H.
$$END$


$$IFN$WDT_OP_MODE.0-1
DATA     SEGMENT
WDTseq   dw   0F01EH
         dw   00FE1H
DATA     ENDS
$$END$

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_WDT Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX
 

$$END$
$$IFN$WDT_OP_MODE.0 || WDT_OP_MODE.1
  _SetEXRegWord WDTRLDL, 0$$WDTRLDL$H   ;Set the reload value.
  _SetEXRegWord WDTRLDH, 0$$WDTRLDH$H
$$END$

$$IFN$WDT_OP_MODE.0-1
  mov  cx,02H         ;Write the LOCKOUT sequence.
  mov  dx,WDTCLR      ;  using 2 sequential writes.
  lea  si,WDTseq
  cld
  cli                 ;Prevent interrupts during writes.
  rep  outsw
  sti                 ;Re-enable interrupts.
$$END$
$$IF$WDT_OP_MODE.1
  _SetEXRegByte WDTSTATUS, 02H    ;Enter the BM mode.
$$IFN$WDT_OP_MODE.0
  _SetEXRegByte WDTSTATUS, 00H    ;Exiting BM mode forces a reload.
$$END$
$$END$
$$IF$WDT_OP_MODE.0 &! WDT_OP_MODE.1
  _SetEXRegByte WDTSTATUS, 01H    ;Disable the WDT.
$$END$
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
  _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_WDT ENDP

_TEXT ENDS
END

##80C386EXCSU#
##80C386EXBIU#
;Initialize Chip Select Unit for:
;  UCS:   $%2CS_BEG_END.0$Start$Ending$ address is @@UCSSTARTX@.
;         Region size is @@UCSLEN@ $%2UCSADL.8$$K$bytes.
;         $%32UCSADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Upper chip select is $%EUCSMSKL.0$.
;         $%2UCSADL.9$8$16$ bit data bus size in $%2UCSADL.8$I/O$memory$ space.
;         External bus ready is $%EUCSADL.7$.
$$IF$UCSADL.10 || UCSMSKL.10
;         SMM region is accessable during $%2UCSADL.10$$SMI access$ $%2UCSMSKL.10$$and memory access$.
$$END$
$$IFN$UCSADL.10 &! UCSMSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS0:   $%2CS_BEG_END.2$Start$Ending$ address is @@CS0STARTX@.
;         Region size is @@CS0LEN@ $%2CS0ADL.8$$K$bytes.
;         $%32CS0ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 0 is $%ECS0MSKL.0$.
;         $%2CS0ADL.9$8$16$ bit data bus size in $%2CS0ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS0ADL.7$.
$$IF$CS0ADL.10 || CS0MSKL.10
;         SMM region is accessable during $%2CS0ADL.10$$SMI access$ $%2CS0MSKL.10$$and memory access$.
$$END$
$$IFN$CS0ADL.10 &! CS0MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS1:   $%2CS_BEG_END.3$Start$Ending$ address is @@CS1STARTX@.
;         Region size is @@CS1LEN@ $%2CS1ADL.8$$K$bytes.
;         $%32CS1ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 1 is $%ECS1MSKL.0$.
;         $%2CS1ADL.9$8$16$ bit data bus size in $%2CS1ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS1ADL.7$.
$$IF$CS1ADL.10 || CS1MSKL.10
;         SMM region is accessable during $%2CS1ADL.10$$SMI access$ $%2CS1MSKL.10$$and memory access$.
$$END$
$$IFN$CS1ADL.10 &! CS1MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS2:   $%2CS_BEG_END.4$Start$Ending$ address is @@CS2STARTX@.
;         Region size is @@CS2LEN@ $%2CS2ADL.8$$K$bytes.
;         $%32CS2ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 2 is $%ECS2MSKL.0$.
;         $%2CS2ADL.9$8$16$ bit data bus size in $%2CS2ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS2ADL.7$.
$$IF$CS2ADL.10 || CS2MSKL.10
;         SMM region is accessable during $%2CS2ADL.10$$SMI access$ $%2CS2MSKL.10$$and memory access$.
$$END$
$$IFN$CS2ADL.10 &! CS2MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS3:   $%2CS_BEG_END.5$Start$Ending$ address is @@CS3STARTX@.
;         Region size is @@CS3LEN@ $%2CS3ADL.8$$K$bytes.
;         $%32CS3ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 3 is $%ECS3MSKL.0$.
;         $%2CS3ADL.9$8$16$ bit data bus size in $%2CS3ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS3ADL.7$.
$$IF$CS3ADL.10 || CS3MSKL.10
;         SMM region is accessable during $%2CS3ADL.10$$SMI access$ $%2CS3MSKL.10$$and memory access$.
$$END$
$$IFN$CS3ADL.10 &! CS3MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS4:  $%2CS_BEG_END.6$Start$Ending$ address is @@CS4STARTX@.
;         Region size is @@CS4LEN@ $%2CS4ADL.8$$K$bytes.
;         $%32CS4ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 4 is $%ECS4MSKL.0$.
;         $%2CS4ADL.9$8$16$ bit data bus size in $%2CS4ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS4ADL.7$.
$$IF$CS4ADL.10 || CS4MSKL.10
;         SMM region is accessable during $%2CS4ADL.10$$SMI access$ $%2CS4MSKL.10$$and memory access$.
$$END$
$$IFN$CS4ADL.10 &! CS4MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS5:   $%2CS_BEG_END.7$Start$Ending$ address is @@CS5STARTX@.
;         Region size is @@CS5LEN@ $%2CS5ADL.8$$K$bytes.
;         $%32CS5ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 5 is $%ECS5MSKL.0$.
;         $%2CS5ADL.9$8$16$ bit data bus size in $%2CS5ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS5ADL.7$.
$$IF$CS5ADL.10 || CS5MSKL.10
;         SMM region is accessable during $%2CS5ADL.10$$SMI access$ $%2CS5MSKL.10$$and memory access$.
$$END$
$$IFN$CS5ADL.10 &! CS5MSKL.10
;         SMM region is accessable during SMI access only.
$$END$
;  CS6:   $%2CS_BEG_END.1$Start$Ending$ address is @@CS6STARTX@.
;         Region size is @@CS6LEN@ $%2CS6ADL.8$$K$bytes.
;         $%32CS6ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
;         Chip select 6 is $%ECS6MSKL.0$.
;         $%2CS6ADL.9$8$16$ bit data bus size in $%2CS6ADL.8$I/O$memory$ space.
;         External bus ready is $%ECS6ADL.7$.
$$IF$CS6ADL.10 || CS6MSKL.10
;         SMM region is accessable during $%2CS6ADL.10$$SMI access$ $%2CS6MSKL.10$$and memory access$.
$$END$
$$IFN$CS6ADL.10 &! CS6MSKL.10
;         SMM region is accessable during SMI access only.
$$END$


INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_CSU Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX
 

$$END$
  _SetEXRegWord UCSADL, 0$$UCSADL$H     ;Configure the upper chip select
  _SetEXRegWord UCSADH, 0$$UCSADH$H
  _SetEXRegWord UCSMSKL, 0$$UCSMSKL$H
  _SetEXRegWord UCSMSKH, 0$$UCSMSKH$H

  _SetEXRegWord CS0ADL, 0$$CS0ADL$H         ;Configure chip select 0
  _SetEXRegWord CS0ADH, 0$$CS0ADH$H
  _SetEXRegWord CS0MSKL, 0$$CS0MSKL$H
  _SetEXRegWord CS0MSKH, 0$$CS0MSKH$H

  _SetEXRegWord CS1ADL, 0$$CS1ADL$H         ;Configure chip select 1
  _SetEXRegWord CS1ADH, 0$$CS1ADH$H
  _SetEXRegWord CS1MSKL, 0$$CS1MSKL$H
  _SetEXRegWord CS1MSKH, 0$$CS1MSKH$H

  _SetEXRegWord CS2ADL, 0$$CS2ADL$H         ;Configure chip select 2
  _SetEXRegWord CS2ADH, 0$$CS2ADH$H
  _SetEXRegWord CS2MSKL, 0$$CS2MSKL$H
  _SetEXRegWord CS2MSKH, 0$$CS2MSKH$H

  _SetEXRegWord CS3ADL, 0$$CS3ADL$H         ;Configure chip select 3
  _SetEXRegWord CS3ADH, 0$$CS3ADH$H
  _SetEXRegWord CS3MSKL, 0$$CS3MSKL$H
  _SetEXRegWord CS3MSKH, 0$$CS3MSKH$H

  _SetEXRegWord CS4ADL, 0$$CS4ADL$H         ;Configure chip select 4
  _SetEXRegWord CS4ADH, 0$$CS4ADH$H
  _SetEXRegWord CS4MSKL, 0$$CS4MSKL$H
  _SetEXRegWord CS4MSKH, 0$$CS4MSKH$H

  _SetEXRegWord CS5ADL, 0$$CS5ADL$H         ;Configure chip select 5
  _SetEXRegWord CS5ADH, 0$$CS5ADH$H
  _SetEXRegWord CS5MSKL, 0$$CS5MSKL$H
  _SetEXRegWord CS5MSKH, 0$$CS5MSKH$H

  _SetEXRegWord CS6ADL, 0$$CS6ADL$H         ;Configure chip select 6
  _SetEXRegWord CS6ADH, 0$$CS6ADH$H
  _SetEXRegWord CS6MSKL, 0$$CS6MSKL$H
  _SetEXRegWord CS6MSKH, 0$$CS6MSKH$H
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
  _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_CSU ENDP

_TEXT ENDS
END


##80C386EX MPLX#
; 
;   Pin Multiplex Configuration Routine
;      (please see Pin Multiplex screen for details) ;
INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
ASSUME CS:_TEXT

Pin_Config Proc Far
$$IF$ P3CFG.0 && INTCFG.5 &! MCR0.3
  ; If connecting INT9 to the Pin, must configure INTCFG, MCR0 (for INT9),
  ; and then finally P3CFG in THAT ORDER.
    _SetEXRegByte INTCFG,  0$$INTCFG$H
    _SetEXRegByte MCR0,    0$$MCR0$H
$$END$    
$$ELSE$
$$IF$ P3CFG.1 && INTCFG.6 &! MCR1.3
  ; If connecting INT8 to the Pin, must configure INTCFG, MCR1 (for INT8),
  ; and then finally P3CFG in THAT ORDER.
    _SetEXRegByte INTCFG,  0$$INTCFG$H
    _SetEXRegByte MCR1,    0$$MCR1$H
$$END$ 
$$END$   

_SetEXRegByte PINCFG, 0$$PINCFG$H
_SetEXRegByte P1CFG, 0$$P1CFG$H
_SetEXRegByte P2CFG, 0$$P2CFG$H
_SetEXRegByte P3CFG, 0$$P3CFG$H
RET
Pin_Config ENDP

_TEXT ENDS
END