386exa.cod

mcs51,2051,x86系列MCU

Send_DMA0_SW_Req Proc Far
     _SetEXRegByte DMASRR$%2REMAPCFG.2$DOS$$, 04H ;Send a software request
RET
Send_DMA0_SW_Req ENDP

_TEXT ENDS
END
##80C386EX DMA1#
;Initialize DMA Channel 1 for:
;  DMA channel 1 is mapped in slot $%2REMAPCFG.2$0$15$.
;
$$IF$ DMA1MSK.2
;  DMA channel 1 is unsynchronized, responding to software requests only.
;  Synchronizing source will be $%6DMACFG.4-6$external (DRQ1)$SIO-1 receiver$SIO-0 transmitter$SSIO receiver$timer 2$unSynchronized$ if hardware requests are enabled.
$$END$
$$IFN$ DMA1MSK.2
;  Synchronizing source is $%6DMACFG.4-6$external (DRQ1)$SIO-1 receiver$SIO-0 transmitter$SSIO receiver$timer 2$unSynchronized$.
$$END$
;  Hardware requests are $%2DMA1MSK.2$enabled$disabled$.
;  Operating mode is $%4DMA1MOD1.6-7$demand transfer$single transfer$block$cascade$ mode.
$$IF$ DMACMD1.4
;  Priority is configured as rotating priority.
$$END$
$$IFN$ DMACMD1.4
;  The priority is set with $%3DMACMD2.2-3$channel 0$channel 1$ external bus master$ lowest.
$$END$  
$$IFN$ DMACFG.5 || DMACFG.4
;  The source (requester) address 0$$DMA1REQ2/3$:$$DMA1REQ0/1$H.
;  Source (requester) addressing is from $%2DMA1MOD2.6$memory$I/O$ space.
;  The source (requester) is performing $%2DMA1BSR.6$word$byte$ transfers.
$$IF$ DMA1MOD2.4
;  The source (requester) address is held constant.
$$END$
$$IFN$ DMA1MOD2.4 && DMA1MOD2.3 && DMAOVFE.3
;  The source (requester) address has all bits decremented.
$$END$
$$IFN$ DMA1MOD2.4 && DMA1MOD2.3 &! DMAOVFE.3
;  The source (requester) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA1MOD2.4 &! DMA1MOD2.3 && DMAOVFE.3
;  The source (requester) address has all bits incremented.
$$END$
$$IFN$ DMA1MOD2.4 &! DMA1MOD2.3 &! DMAOVFE.3
;  The source (requester) address has the low 16 bits incremented.
$$END$
;  The destination (target) address 0$$DMA1TAR2/3$:$$DMA1TAR0/1$H.
;  Destination (target) addressing is to $%2DMA1MOD2.5$memory$I/O$ space.
;  The destination (target) is performing $%2DMA1BSR.4$word$byte$ transfers.
$$IF$ DMA1MOD2.2
;  The destination (target) address is held constant.
$$END$
$$IFN$ DMA1MOD2.2 && DMA1MOD1.5 && DMAOVFE.2
;  The destination (target) address has all bits decremented.
$$END$
$$IFN$ DMA1MOD2.2 && DMA1MOD1.5 &! DMAOVFE.2
;  The destination (target) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA1MOD2.2 &! DMA1MOD1.5 && DMAOVFE.2
;  The destination (target) address has all bits incremented.
$$END$
$$IFN$ DMA1MOD2.2 &! DMA1MOD1.5 &! DMAOVFE.2
;  The destination (target) address has the low 16 bits incremented.
$$END$
$$END$
$$IF$ DMACFG.5 &! DMACFG.4
;  The source (target) address 0$$DMA1TAR2/3$:$$DMA1TAR0/1$H.
;  Source (target) addressing is from $%2DMA1MOD2.5$memory$I/O$ space.
;  The source (target) is performing $%2DMA1BSR.4$word$byte$ transfers.
$$IF$ DMA1MOD2.2
;  The source (target) address is held constant.
$$END$
$$IFN$ DMA1MOD2.2 && DMA1MOD1.5 && DMAOVFE.2
;  The source (target) address has all bits decremented.
$$END$
$$IFN$ DMA1MOD2.2 && DMA1MOD1.5 &! DMAOVFE.2
;  The source (target) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA1MOD2.2 &! DMA1MOD1.5 && DMAOVFE.2
;  The source (target) address has all bits incremented.
$$END$
$$IFN$ DMA1MOD2.2 &! DMA1MOD1.5 &! DMAOVFE.2
;  The source (target) address has the low 16 bits incremented.
$$END$
;  The destination (requester) address 0$$DMA1REQ2/3$:$$DMA1REQ0/1$H.
;  Destination (requester) addressing is to $%2DMA1MOD2.6$memory$I/O$ space.
;  The destination (requester) is performing $%2DMA1BSR.6$word$byte$ transfers.
$$IF$ DMA1MOD2.4
;  The destination (requester) address is held constant.
$$END$
$$IFN$ DMA1MOD2.4 && DMA1MOD2.3 && DMAOVFE.3
;  The destination (requester) address has all bits decremented.
$$END$
$$IFN$ DMA1MOD2.4 && DMA1MOD2.3 &! DMAOVFE.3
;  The destination (requester) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA1MOD2.4 &! DMA1MOD2.3 && DMAOVFE.3
;  The destination (requester) address has all bits incremented.
$$END$
$$IFN$ DMA1MOD2.4 &! DMA1MOD2.3 &! DMAOVFE.3
;  The destination (requester) address has the low 16 bits incremented.
$$END$
$$END
$$IFN$ DMA1MOD1.6 |! DMA1MOD1.7
;  The transfer type is $%3DMA1MOD1.2-3$verify$write$read$.
$$END$
$$IF$ DMA1MOD1.6 && DMA1MOD1.7
;  The transfer type is N/A in cascade mode.
$$END$
;  The transfer count is 0$$DMA1BYC2$:$$DMA1BYC0/1$H.
;  The sampling configuration is $%4DMACMD2.0-1$DREQ and EOP asynchronous$DREQ synchronous, EOP asynchronous$DREQ asynchronous, EOP synchronous$DREQ and EOP synchronous$.
;  The transfer rate is $%2DMA1MOD2.7$1 cycle (fly by)$2 cycles$.
;  The channel is $%EDMAGRPMSK.1$.
;  Chaining is $%EDMA1CHR.2$.
;  Auto-initialization is $%EDMA1MOD1.4$.
;  The TC interrupt is $%EDMAIEN.1$.
$$IFN$ PINCFG.3 |! PINCFG.2
;  External connections are made to $%4PINCFG.2-3$EOP and DACK$EOP$DACK$$.
$$END$
$$IF$ PINCFG.3 && PINCFG.2
;  No external connections are made.
$$END$
:
;Note: Call "Send_DMA1_SW_Req" to initiate a software DMA Request.

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

  Init_DMA1 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
    MOV   AX, 08000H       ;Enable expanded I/O space
    OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
    XCHG  AL, AH
    OUT   REMAPCFGL, AL
    OUT   REMAPCFG, AX
   

$$END$
    _SetEXRegByte DMACFG, 0$$DMACFG$H
    _SetEXRegByte DMACMD1, 0$$DMACMD1$H
    _SetEXRegByte DMACMD2, 0$$DMACMD2$H
    _SetEXRegByte DMAMOD1, 0$$DMA1MOD1$H
    _SetEXRegByte DMAMOD2, 0$$DMA1MOD2$H
    _SetEXRegByte DMASRR, 0$$DMA1SRR$H
    _SetEXRegByte DMABSR, 0$$DMA1BSR$H
    _SetEXRegByte DMACHR, 0$$DMA1CHR$H
    _SetEXRegByte DMAIEN, 0$$DMAIEN$H
    _SetEXRegByte DMAOVFE, 0$$DMAOVFE$H
    _SetEXRegByte PINCFG, 0$$PINCFG$H  ;Setup pin connections

    _SetEXRegByte DMACLRBP, 0               ;Clear the byte pointer flip-flop

    _SetEXRegByte DMA1TAR0_1, 0$$DMA1TAR0/1.0-7$H           ;Write target address, bits 0-7
    _SetEXRegByte DMA1TAR0_1, 0$$DMA1TAR0/1.8-15$H           ;Write target address, bits 8-15
    _SetEXRegByte DMA1TAR2, 0$$DMA1TAR2/3.0-7$H             ;Write target address, bits 16-23
    _SetEXRegByte DMA1TAR3, 0$$DMA1TAR2/3.8-15$H             ;Write target address, bits 24-25
     
    _SetEXRegByte DMA1BYC0_1, 0$$DMA1BYC0/1.0-7$H           ;Write count, bits 0-7
    _SetEXRegByte DMA1BYC0_1, 0$$DMA1BYC0/1.8-15$H           ;Write count, bits 8-15
    _SetEXRegByte DMA1BYC2, 0$$DMA1BYC2$H             ;Write count, bits 16-23

    _SetEXRegByte DMA1REQ0_1, 0$$DMA1REQ0/1.0-7$H           ;Write requester address, bits 0-7
    _SetEXRegByte DMA1REQ0_1, 0$$DMA1REQ0/1.8-15$H           ;Write requester address, bits 8-15
    _SetEXRegByte DMA1REQ2_3, 0$$DMA1REQ2/3.0-7$H           ;Write requester address, bits 16-23
    _SetEXRegByte DMA1REQ2_3, 0$$DMA1REQ2/3.8-15$H           ;Write requester address, bits 24-25

    _SetEXRegByte DMAMSK, 0$$DMA1MSK$H
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
    _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_DMA1 ENDP

Send_DMA1_SW_Req Proc Far
    _SetEXRegByte DMASRR$%2REMAPCFG.2$DOS$$, 05H ;Send a software request
RET
Send_DMA1_SW_Req ENDP

_TEXT ENDS
END
##80C386EXTimer0#
;Initialize Timer 0 for:
;  Timer 0 is mapped in slot $%2REMAPCFG.0$0$15$.
;
;  Timer mode $%8TMRCON0.1-3$0 (Interrupt on TC)$1 (Hardware retriggerable 1 shot)$2 (Rate generator mode)$3 (Square wave mode)$4 (Software triggered strobe)$5 (Hardware triggered strobe)$2 (Rate generator mode)$3 (Square wave mode)$.
;  Timer count of $$TMR0_COUNT$$%2TMRCON0.0$H (Binary)$ BCD$.
;  $%2TMRCFG.0$Internal$External$ clock source.
;  Gate source is $%2TMRCFG.1$Vcc$external$.
;  Timer output is $%2P3CFG.0$internal only$internal and external$.

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

  Init_TCU0 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
    MOV   AX, 08000H       ;Enable expanded I/O space
    OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
    XCHG  AL, AH
    OUT   REMAPCFGL, AL
    OUT   REMAPCFG, AX
   

$$END$
    _SetEXRegByte P3CFG, 0$$P3CFG$H   ;Set the output location.
    _SetEXRegByte TMRCFG, 0$$TMRCFG$H    ;Set input sources.
    _SetEXRegByte TMRCON$%2REMAPCFG.0$DOS$$, 0$$TMRCON0$H   ;Set timer parameters.
    _SetEXRegByte TMR0$%2REMAPCFG.0$DOS$$, 0$$TMR0_COUNT.0-7$H     ;Set the timer count (LO byte).
    _SetEXRegByte TMR0$%2REMAPCFG.0$DOS$$, 0$$TMR0_COUNT.8-15$H     ;Set the timer count (HI byte).
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
    _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
  Init_TCU0 ENDP

_TEXT ENDS
END

##80C386EXTimer1#
;Initialize Timer 1 for:
;  Timer 1 is mapped in slot $%2REMAPCFG.0$0$15$.
;
;  Timer mode $%8TMRCON1.1-3$0 (Interrupt on TC)$1 (Hardware retriggerable 1 shot)$2 (Rate generator mode)$3 (Square wave mode)$4 (Software triggered strobe)$5 (Hardware triggered strobe)$2 (Rate generator mode)$3 (Square wave mode)$.
;  Timer count of $$TMR1_COUNT$$%2TMRCON1.0$H (Binary)$ BCD$.
;  $%2TMRCFG.2$Internal$External$ clock source.
;  Gate source is $%2TMRCFG.3$Vcc$external$.
;  Timer output is $%2P3CFG.1$internal only$internal and external$.

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

  Init_TCU1 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
    MOV   AX, 08000H       ;Enable expanded I/O space
    OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
    XCHG  AL, AH
    OUT   REMAPCFGL, AL
    OUT   REMAPCFG, AX
   

$$END$
    _SetEXRegByte P3CFG, 0$$P3CFG$H   ;Set the output location.
    _SetEXRegByte TMRCFG, 0$$TMRCFG$H    ;Set input sources.
    _SetEXRegByte TMRCON$%2REMAPCFG.0$DOS$$, 0$$TMRCON1$H   ;Set timer parameters.
    _SetEXRegByte TMR1$%2REMAPCFG.0$DOS$$, 0$$TMR1_COUNT.0-7$H     ;Set the timer count (LO byte).
    _SetEXRegByte TMR1$%2REMAPCFG.0$DOS$$, 0$$TMR1_COUNT.8-15$H     ;Set the timer count (HI byte).
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
    _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
  Init_TCU1 ENDP

_TEXT ENDS
END

##80C386EXTimer2#
;Initialize Timer 2 for:
;  Timer 2 is mapped in slot $%2REMAPCFG.0$0$15$.
;
;  Timer mode $%8TMRCON2.1-3$0 (Interrupt on TC)$1 (Hardware retriggerable 1 shot)$2 (Rate generator mode)$3 (Square wave mode)$4 (Software triggered strobe)$5 (Hardware triggered strobe)$2 (Rate generator mode)$3 (Square wave mode)$.
;  Timer count of $$TMR2_COUNT$$%2TMRCON2.0$H (Binary)$ BCD$.
;  $%2TMRCFG.4$Internal$External$ clock source.
;  Gate source is $%2TMRCFG.5$Vcc$external$.
;  Timer output is $%2PINCFG.5$internal only$internal and external$.

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

  Init_TCU2 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
    MOV   AX, 08000H       ;Enable expanded I/O space
    OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
    XCHG  AL, AH
    OUT   REMAPCFGL, AL
    OUT   REMAPCFG, AX
   

$$END$
    _SetEXRegByte PINCFG, 0$$PINCFG$H   ;Set the output location.
    _SetEXRegByte TMRCFG, 0$$TMRCFG$H    ;Set input sources.
    _SetEXRegByte TMRCON$%2REMAPCFG.0$DOS$$, 0$$TMRCON2$H   ;Set timer parameters.
    _SetEXRegByte TMR2$%2REMAPCFG.0$DOS$$, 0$$TMR2_COUNT.0-7$H     ;Set the timer count (LO byte).
    _SetEXRegByte TMR2$%2REMAPCFG.0$DOS$$, 0$$TMR2_COUNT.8-15$H     ;Set the timer count (HI byte).
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
    _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
  Init_TCU2 ENDP

_TEXT ENDS
END

##80C386EX Serial0#
;Initialize the Asynchronous Serial Port #0 for:
;  Serial port 0 is mapped in slot $%2REMAPCFG.0$0$15$.
;
;  Word length of $%4LCR0.0-1$5$6$7$8$ bits.
;  $%8LCR0.3-5$No$Odd$$Even$$Zero$$Mark$ parity.
;  $%2SIOCFG.0$External$Internal$ clocking.
$$IF$SIOCFG.0
;  @@CPU_FREQ@ MHz clocking frequency.
$$END$
$$IFN$SIOCFG.0
;  @@COMCLKFREQ@ MHz clocking frequency.
$$END$
$$IFN$LCR0.0-1
;  $%2LCR0.2$1 stop bit$1.5 stop bits$.
$$END$
$$IF$LCR0.0-1
;  $%2LCR0.2$1 stop bit$2 stop bits$.
$$END$
;  $%2SIOCFG.6$External$Internal$ modem control sources.
;  @@SIO0BAUDRATE@(@@SIO0BAUDERROR@%) bps baud rate.
;  Interrupt sources:
$$IFN$IER0.0-3
;                None Enabled
$$END$
$$IF$IER0.0
;                Reception Complete Interrupt
$$END$
$$IF$IER0.1
;                Transmission Register Empty Interrupt
$$END$
$$IF$IER0.2
;                Receive Line Status Interrupt
$$END$
$$IF$IER0.3
;                Modem Status Interrupt
$$END$

INCLUDE 80386EX.INC
_TEXT SEGMENT PUBLIC 'CODE'
  ASSUME CS:_TEXT

Init_SIO0 Proc Far
$$IFN$ REMAPCFG.15

; Enable expanded I/O space for peripheral initialization.
  MOV   AX, 08000H       ;Enable expanded I/O space
  OUT   REMAPCFGH, AL    ;  and unlock the re-map bits
  XCHG  AL, AH
  OUT   REMAPCFGL, AL
  OUT   REMAPCFG, AX
 

$$END$
  _SetEXRegByte SIOCFG, 0$$SIOCFG$H    ;Set clocking and modem control sources.
  _SetEXRegByte LCR0$%2REMAPCFG.5$DOS$$, 080H     ;Access divisor latch.
  _SetEXRegByte DLH0$%2REMAPCFG.5$DOS$$, 0$$DLH0$H      ;Set the divisor for the baud rate generator.
  _SetEXRegByte DLL0$%2REMAPCFG.5$DOS$$, 0$$DLL0$H
  _SetEXRegByte LCR0$%2REMAPCFG.5$DOS$$, 0$$LCR0$H      ;Set parity, stop bits, and word size.
  _SetEXRegByte IER0$%2REMAPCFG.5$DOS$$, 0$$IER0$H      ;Enable selected interrupts.

  MOV DX, IIR0$%2REMAPCFG.5$DOS$$                 ;Clear all interrupts at start.
  IN  AL, DX

  _SetEXRegByte P1CFG, 0$$P1CFG$H   ;Set PxCFG registers to set signal paths.
  _SetEXRegByte P2CFG, 0$$P2CFG$H
  _SetEXRegByte P3CFG, 0$$P3CFG$H
$$IFN$ REMAPCFG.15

; Restore I/O space to original condition.
  _SetEXRegByte REMAPCFGH, 00H  ;Disables expanded I/O space
$$END$
RET
Init_SIO0 ENDP

_TEXT ENDS
END

##80C386EX Serial1#
;Initialize the Asynchronous Serial Port #1 for:
;  Serial port 1 is mapped in slot $%2REMAPCFG.0$0$15$.
;
;  Word length of $%4LCR1.0-1$5$6$7$8$ bits.
;  $%8LCR1.3-5$No$Odd$$Even$$Zero$$Mark$ parity.
;  $%2SIOCFG.1$External$Internal$ clocking.
$$IF$SIOCFG.1
;  @@CPU_FREQ@ MHz clocking frequency.
$$END$
$$IFN$SIOCFG.1
;  @@COMCLKFREQ@ MHz clocking frequency.
$$END$
$$IFN$LCR1.0-1
;  $%2LCR1.2$1 stop bit$1.5 stop bits$.
$$END$
$$IF$LCR1.0-1
;  $%2LCR1.2$1 stop bit$2 stop bits$.
$$END$