support.c

mcs51,2051,x86系列MCU

/* APB_BLOCK_START = COPYRIGHT */
/* Copyright (C) Intel Corporation 1994
         All Rights Reserved.

The Software is provided "AS IS."

LIMITATION OF LIABILITY:    NEITHER INTEL NOR ITS VENDORS OR AGENTS 
    SHALL BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, 
    INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR 
    CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR 
    OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
*/
/* APB_BLOCK_END */

/* APB_BLOCK_START = INCLUDE_STATEMENTS */
#include <conio.h>
#include <string.h>
#include <DOS.h>

#include "80386ex.h"
#include "EV386EX.h"
#include "support.h"
/* APB_BLOCK_END */


/* APB_BLOCK_START = SIO */
int Tbuffer_index = 0; 
char trans_buffer[1024];
char rec_buffer;
/* APB_BLOCK_END */


/* APB_BLOCK_START = GLOBALS */

    /* Globals For information about the ICU */
BYTE    _IRQ_SlaveBase_= 0x30;
BYTE    _IRQ_MstrBase_ = 0x20;
BYTE    _CascadeBits_  = 0x4;

/* APB_BLOCK_END */

/* APB_BLOCK_START = ICU_SUBROUTINES */
/* InitICU
   Description:
      Initialization for both the master and slave Interrupt Control Units (ICU).  This
      routine only initializes the internal interrupt controllers, external ICUs must be
      initialized separatly.  These should be initialized before interrupts are enabled
      (i.e. enable()).
   
   Parameters:
      MstrMode       Mode of operation for Master ICU
      MstrBase    Specifies the base interrupt vector number for the Master interrupts.
                  For example, if IR1 of the master goes active and the MstrBase = 0x20
                  the processor will use interrupt vector table entry 0x21.
      MstrCascade     Which Master IRQs are used for Slave ICUs.
      SlaveMode      Mode of operation for Slave ICU
      SlaveBase      Specifies the base interrupt vector number for the Slave interrupts.
                  For example, if IR1 of the slave goes active and the SlaveBase = 0x40
                  the processor will use interrupt vector table entry 0x41.
       MstrPins      Defines what EX pins are avaliable externally to the chip for the Master.
       SlavePins     Defines what EX pins are avaliable externally to the chip for the Slave.
   Returns: Error Code
      E_OK  -- Initialized OK, No error.

   Assumptions:
      REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
      
   Real/Protected Mode
      No changes required.
*/
int InitICU(BYTE MstrMode, BYTE MstrBase, BYTE MstrCascade, BYTE SlaveMode, BYTE SlaveBase,BYTE MstrPins, BYTE SlavePins)
{
  BYTE   icw, cfg_pins;
      /* Program Slave ICU */
  _IRQ_SlaveBase_ = SlaveBase & 0xf8;
  _SetEXRegByte(ICW1S, 0x11 | SlaveMode);       /* Set slave triggering */
  _SetEXRegByte(ICW2S, _IRQ_SlaveBase_);     /* Set slave base interrupt type, least 3-bit must be 0 */
  _SetEXRegByte(ICW3S, 0x2);              /* Set slave ID */
  _SetEXRegByte(ICW4S, 0x1);              /* Set bit 0 to guarantee operation*/
      /* Program Master ICU */
  _IRQ_MstrBase_ = MstrBase & 0xf8;
  _CascadeBits_  = MstrCascade | 0x4;
  icw = (MstrMode & ICU_TRIGGER_LEVEL) ? 0x19 : 0x11;
  _SetEXRegByte(ICW1M, icw);                 /* Set master triggering */
  _SetEXRegByte(ICW2M, _IRQ_MstrBase_);      /* Set master base interrupt type, least 3-bit must be 0 */
  _SetEXRegByte(ICW3M, _CascadeBits_);       /* Set master cascade pins, Make sure IR2 set for Cascade */
  icw = (MstrMode & ~ICU_TRIGGER_LEVEL) | 1; /* Set bit 0 and remove Trigger_level bit (part of ICW1) */
  _SetEXRegByte(ICW4M, icw);                 /* Set slave IDs in master */

      /* Program chip configuration registers */
  cfg_pins = _GetEXRegByte(INTCFG);
  if( (MstrCascade & 0xfb) != 0 )            /* bit 2 (IR2) is internal, external signals not required for just IR2 */
   cfg_pins |= 0x80;                      /* Using external slaves, therefore enable Cascade signals */
  cfg_pins |= SlavePins;
  _SetEXRegByte(INTCFG, SlavePins);             /* Set Slave external interrupt pins */
  cfg_pins = _GetEXRegByte(P3CFG);           /* Preserve other set bits */
  _SetEXRegByte(P3CFG, cfg_pins | MstrPins); /* Set Master external interrupt pins */

  return E_OK;
}
/* APB_BLOCK_END */

/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/

/* APB_BLOCK_START = ICU_SLAVE_ROUTINE */
/* InitICUSlave
   Description:
      Initialization only the internal slave Interrupt Control Units (ICU).  This
      routine only initializes the internal interrupt controller, external ICUs must be
      initialized separatly.
   
   Parameters:
      SlaveMode      Mode of operation for Slave ICU
      SlaveBase      Specifies the base interrupt vector number for the Slave interrupts.
                  For example, if IR1 of the slave goes active and the SlaveBase = 0x40
                  the processor will use interrupt vector table entry 0x41.
       SlavePins     Defines what EX pins are avaliable externally to the chip for the Slave.
   Returns: Error Code
      E_OK  -- Initialized OK, No error.

   Assumptions:
      REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
      
   Real/Protected Mode
      No changes required.
*/
int InitICUSlave(BYTE SlaveMode, BYTE SlaveBase, BYTE SlavePins)
{
  BYTE   cfg_pins;
      /* Program Slave ICU */
  _IRQ_SlaveBase_ = SlaveBase & 0xf8;
  _SetEXRegByte(ICW1S, 0x11 | SlaveMode);       /* Set slave triggering */
  _SetEXRegByte(ICW2S, _IRQ_SlaveBase_);     /* Set slave base interrupt type, least 3-bit must be 0 */
  _SetEXRegByte(ICW3S, 0x2);              /* Set slave ID */
  _SetEXRegByte(ICW4S, 0x1);              /* Set bit 0 to guarantee operation*/
  cfg_pins = _GetEXRegByte(INTCFG);
  cfg_pins |= SlavePins;
  _SetEXRegByte(INTCFG, SlavePins);             /* Set Slave external interrupt pins */
  
  return E_OK;
}
/* APB_BLOCK_END */

/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/


/* APB_BLOCK_START = INTERRUPTS */
/* Disable8259Interrupt
   Description:
      Disables 8259a interrupts for the master and the slave.
   
   Parameters:
      MstrMask    Mask value for mster ICU
      SlaveMask      Mask value for slave ICU
      
      Each bit location that is set will disable the corresponding interrupt (by
      setting the bit in the interrupt control register).  For example, to disable
      master IR3 and IR5 set MstrMask = 0x28 (bits 3 and 5 are set).
      
   Returns: None

   Assumptions:
      REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
      
   Real/Protected Mode
      No changes required.
*/
void Disable8259Interrupt(BYTE MstrMask, BYTE SlaveMask)
{
   BYTE Mask;
   if(MstrMask != 0)
   {
      Mask = _GetEXRegByte(OCW1M);
      _SetEXRegByte(OCW1M, Mask | MstrMask);
   }
   if(SlaveMask != 0)
   {
      Mask = _GetEXRegByte(OCW1S);
      _SetEXRegByte(OCW1S, Mask | SlaveMask);
   }
}

/* Enable8259Interrupt
   Description:
      Enables 8259a interrupts for the master and the slave.
   
   Parameters:
      MstrMask    Enable mask value for mster ICU
      SlaveMask      Enable mask value for slave ICU
      
      Each bit location that is set will enable the corresponding interrupt (by
      clearing the bit in the interrupt control register).  For example, to enable
      master IR3 and IR5 set MstrMask = 0x28 (bits 3 and 5 are set).
      
   Returns: None

   Assumptions:
      REMAPCFG register has Expanded I/O space access enabled (ESE bit set).
      
   Real/Protected Mode
      No changes required.
*/
void Enable8259Interrupt(BYTE MstrMask, BYTE SlaveMask)
{
   BYTE Mask;
   if(MstrMask != 0)
   {
      Mask = _GetEXRegByte(OCW1M);
      _SetEXRegByte(OCW1M, Mask & (~MstrMask));
   }
   if(SlaveMask != 0)
   {
      Mask = _GetEXRegByte(OCW1S);
      _SetEXRegByte(OCW1S, Mask & (~SlaveMask));
   }
}
/* APB_BLOCK_END */

/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/
/******************************************************************************************************************/


/* APB_BLOCK_START = VECTORS */
/* SetIRQVector
   Description:
      Loads the interrupt vector table with the address of the interrupt routine.  The vector
      table entry number is determined by the vector number.
   
   Parameters:
      InterProc      Address of interrupt function, will be loaded into the interrupt table.
      IRQ            Hardware Interrupt request number (0-15).
      ISR_Type    Specifies if the interrupt function should be treated as a TRAP_ISR
                  or an INTERRUPT_ISR.  Real Mode only supports INTERRUPT_ISR
                  (parameter is ignored).  Protected mode   supports both.
   
   Returns: Error Code
      E_INVALID_VECTOR    - An IRQ of greater than 15 was passed
      E_BADVECTOR         - IRQ is used for cascading to a slave interrupt controller
      E_OK           -- Initialized OK, No error.
   Assumptions:
      Compiler supports far and interrupt keywords

      ICU must be configured before this function is call for it to operate properly

      _IRQ_SlaveBase_,_IRQ_MstrBase_,_CascadeBits_ are set before function is called.
      These are initialized in the InitICU functions supplied in this source.
      
   Real/Protected Mode
      No changes required.  Uses SetInterruptVector which is mode dependant(separate source)
*/
int SetIRQVector( void (far interrupt *IntrProc)(void), int IRQ, int IntrType)
{
   int Vector;
   
   if(IRQ > 15) return E_INVALID_VECTOR;
   
   if(IRQ > 7)    /* Get Vector from Slave */
      Vector = _IRQ_SlaveBase_ + IRQ - 8;
   else        /* From Master */
   {
      if((1 << IRQ) & _CascadeBits_) return E_BADVECTOR;
      Vector = _IRQ_MstrBase_ + IRQ;
   }

    SetInterruptVector(IntrProc, Vector, IntrType);
   return E_OK;
}


/*	SetInterruptVector
	Description:
		Loads the interrupt vector table with the address of the interrupt routine.  The vector
		table entry number is determined by the vector number.
	
	Parameters:
		InterProc		Address of interrupt function, will be loaded into the interrupt table.
		ISR_Type		Specifies if the interrupt function.  Real Mode only supports 
						INTERRUPT_ISR (the parameter is ignored).  The prameter is kept to maintain
						compatibilty with the protected mode version of this function.
	
	Returns:	None

	Assumptions:
		Compiler supports far and interrupt keywords
		Compiler may issue a warning about IntrType not used.  IntrType is kept for protected mode
		compatibilty.
		
	Real/Protected Mode
		Real Mode only, see pSetIntr.c for protected mode version
*/
void SetInterruptVector( void (far interrupt *IntrProc)(void), int Vector, int IntrType)
{