386exc.cod

mcs51,2051,x86系列MCU

##80C386EX Serial1#
/* 
Initialize the Asynchronous Serial Port #1 for:
  Serial port 1 is mapped in slot $%2REMAPCFG.0$0$15$.

  Word length of $%4LCR1.0-1$5$6$7$8$ bits
  $%8LCR1.3-5$No$Odd$$Even$$Zero$$Mark$ parity
  $%2SIOCFG.1$External$Internal$ clocking
$$IF$SIOCFG.1
  @@CPU_FREQ@ MHz clocking frequency
$$END$
$$IFN$SIOCFG.1
  @@COMCLKFREQ@ MHz clocking frequency
$$END$
$$IFN$LCR1.0-1
  $%2LCR1.2$1 stop bit$1.5 stop bits$
$$END$
$$IF$LCR1.0-1
  $%2LCR1.2$1 stop bit$2 stop bits$
$$END$
  $%2SIOCFG.7$External$Internal$ modem control sources
  @@SIO1BAUDRATE@(@@SIO1BAUDERROR@%) bps baud rate
  Interrupt sources:
$$IFN$IER1.0-3
                None Enabled
$$END$
$$IF$IER1.0
                Reception Complete Interrupt
$$END$
$$IF$IER1.1
                Transmission Register Empty Interrupt
$$END$
$$IF$IER1.2
                Receive Line Status Interrupt
$$END$
$$IF$IER1.3
                Modem Status Interrupt
$$END$
*/

#include "80386EX.h"
void Init_SIO1(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
  _SetEXRegByte(SIOCFG, 0x$$SIOCFG$);   /* Set clocking and modem control sources. */
  _SetEXRegByte(LCR1$%2REMAPCFG.6$DOS$$, 0x80);    /* Access divisor latch. */
  _SetEXRegByte(DLH1$%2REMAPCFG.6$DOS$$, 0x$$DLH1$);     /* Set the divisor for the baud rate generator. */
  _SetEXRegByte(DLL1$%2REMAPCFG.6$DOS$$, 0x$$DLL1$);
  _SetEXRegByte(LCR1$%2REMAPCFG.6$DOS$$, 0x$$LCR1$);     /* Set parity, stop bits, and word size. */
  _SetEXRegByte(IER1$%2REMAPCFG.6$DOS$$, 0x$$IER1$);     /* Enable selected interrupts. */
  _GetEXRegByte(IIR1$%2REMAPCFG.5$DOS$$);          /* Clear all interrupts at start. */
_SetEXRegByte(P3CFG, 0x$$P3CFG$);  /* Set P3CFG ans PINCFG registers to set signal paths. */
  _SetEXRegByte(PINCFG, 0x$$PINCFG$);
$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}

##80C386EX CPU#
/* 
  Enabling expanded I/O space requires 3 immediately
  sequential write statements, which cannot be done in 'C'.

  Any changes to the CPU addressing must be done
  in assembly language.
*/
##80C386EX RCU#
/* 
Initialize the Refresh Control Unit for:
  Refresh address of @@REF_ADDRESS@000H.
  Refresh gate between rows is @@REF_TIME@uSec.
  Using a CPU frequency of @@CPU_FREQ@.
  The refresh control unit is $%ERFSCON.15$.
  The external pin is connected to $%2PINCFG.6$CS6#$REFRESH#$.
*/

#include "80386EX.h"
void Init_RCU(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
  _SetEXRegByte(PINCFG, 0x$$PINCFG$);  /* Program external pin function. */
  _SetEXRegWord(RFSCIR, 0x$$RFSCIR$);  /* Program refresh interval. */
  _SetEXRegWord(RFSBAD, 0x$$RFSBAD$);  /* Program base address. */
  _SetEXRegWord(RFSADD, 0x$$RFSADD$);  /* Program address register. */
  _SetEXRegWord(RFSCON, 0x$$RFSCON$);  /* Program the enable bit. */
$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}
##80C386EX WDT#
/* 
Initialize the Watch Dog Timer for:
  Watch Dog Timer Status = $%4WDT_OP_MODE.0-1$Software Watchdog$Disabled$General Purpose Timer$Bus Monitor Mode$
$$IFN$WDT_OP_MODE.1
  WDT Reload Value = 0$$WDTRLDH$:$$WDTRLDL$H
$$END$
$$IF$WDT_OP_MODE.0-1
*/

#include "80386EX.h"
void Init_WDT(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
$$IFN$WDT_OP_MODE.0 || WDT_OP_MODE.1
  _SetEXRegWord(WDTRLDL, 0x$$WDTRLDL$);  /* Set the reload value. */
  _SetEXRegWord(WDTRLDH, 0x$$WDTRLDH$);
$$END$

$$IF$WDT_OP_MODE.1
  _SetEXRegByte(WDTSTATUS, 0x2);   /* Enter the BM mode. */
$$IFN$WDT_OP_MODE.0
  _SetEXRegByte(WDTSTATUS, 0x0);   /* Exiting BM mode forces a reload. */
$$END$
$$END$
$$IF$WDT_OP_MODE.0 &! WDT_OP_MODE.1
  _SetEXRegByte(WDTSTATUS, 0x1);   /* Disable the WDT. */
$$END$
$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}
$$END$
$$IFN$WDT_OP_MODE

  Enabling the Watch Dog Timer requires sequential
  word writes of the LOCKOUT sequence, which can
  be done in inline assembly using 'C'.
   
  If the compiler being used does not support inline
  assembly then the LOCKOUT sequence must be 
  programmed using assembly language only.
*/

#include "80386EX.h"
void Init_WDT(void)
{
unsigned long WDTseq = 0x0FE1F01E;
$$IFN$ REMAPCFG.15

/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();
$$END$

  _SetEXRegWord(WDTRLDL, 0x$$WDTRLDL$);  /* Set the reload value. */
  _SetEXRegWord(WDTRLDH, 0x$$WDTRLDH$);

  _asm mov cx, 02H;                   /* Write the LOCKOUT sequence */
  _asm mov dx, WDTCLR;                /*   using 2 sequential writes.*/
  _asm lea si, WDTseq;
  _asm cld;
  _asm cli;                           /*prevent interrupts during writes.*/
  _asm rep outsw;
  _asm sti;                           /*Re-enable interrupts. */
$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}
$$END$
##80C386EXCSU#
##80C386EXBIU#
/* 
Initialize Chip Select Unit for:
  UCS:   $%2CS_BEG_END.0$Start$Ending$ address is @@UCSSTARTX@.
         Region size is @@UCSLEN@ $%2UCSADL.8$$K$bytes.
         $%32UCSADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%EUCSMSKL.0$.
         $%2UCSADL.9$8$16$ bit data bus size in $%2UCSADL.8$I/O$memory$ space.
         External bus ready is $%EUCSADL.7$.
$$IF$UCSADL.10 || UCSMSKL.10
         SMM region is accessable during $%2UCSADL.10$$SMI access$ $%2UCSMSKL.10$$and memory access$.
$$END$
$$IFN$UCSADL.10 &! UCSMSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS0:   $%2CS_BEG_END.2$Start$Ending$ address is @@CS0STARTX@.
         Region size is @@CS0LEN@ $%2CS0ADL.8$$K$bytes.
         $%32CS0ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS0MSKL.0$.
         $%2CS0ADL.9$8$16$ bit data bus size in $%2CS0ADL.8$I/O$memory$ space.
         External bus ready is $%ECS0ADL.7$.
$$IF$CS0ADL.10 || CS0MSKL.10
         SMM region is accessable during $%2CS0ADL.10$$SMI access$ $%2CS0MSKL.10$$and memory access$.
$$END$
$$IFN$CS0ADL.10 &! CS0MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS1:   $%2CS_BEG_END.3$Start$Ending$ address is @@CS1STARTX@.
         Region size is @@CS1LEN@ $%2CS1ADL.8$$K$bytes.
         $%32CS1ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS1MSKL.0$.
         $%2CS1ADL.9$8$16$ bit data bus size in $%2CS1ADL.8$I/O$memory$ space.
         External bus ready is $%ECS1ADL.7$.
$$IF$CS1ADL.10 || CS1MSKL.10
         SMM region is accessable during $%2CS1ADL.10$$SMI access$ $%2CS1MSKL.10$$and memory access$.
$$END$
$$IFN$CS1ADL.10 &! CS1MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS2:   $%2CS_BEG_END.4$Start$Ending$ address is @@CS2STARTX@.
         Region size is @@CS2LEN@ $%2CS2ADL.8$$K$bytes.
         $%32CS2ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS2MSKL.0$.
         $%2CS2ADL.9$8$16$ bit data bus size in $%2CS2ADL.8$I/O$memory$ space.
         External bus ready is $%ECS2ADL.7$.
$$IF$CS2ADL.10 || CS2MSKL.10
         SMM region is accessable during $%2CS2ADL.10$$SMI access$ $%2CS2MSKL.10$$and memory access$.
$$END$
$$IFN$CS2ADL.10 &! CS2MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS3:   $%2CS_BEG_END.5$Start$Ending$ address is @@CS3STARTX@.
         Region size is @@CS3LEN@ $%2CS3ADL.8$$K$bytes.
         $%32CS3ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS3MSKL.0$.
         $%2CS3ADL.9$8$16$ bit data bus size in $%2CS3ADL.8$I/O$memory$ space.
         External bus ready is $%ECS3ADL.7$.
$$IF$CS3ADL.10 || CS3MSKL.10
         SMM region is accessable during $%2CS3ADL.10$$SMI access$ $%2CS3MSKL.10$$and memory access$.
$$END$
$$IFN$CS3ADL.10 &! CS3MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS4:   $%2CS_BEG_END.6$Start$Ending$ address is @@CS4STARTX@.
         Region size is @@CS4LEN@ $%2CS4ADL.8$$K$bytes.
         $%32CS4ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS4MSKL.0$.
         $%2CS4ADL.9$8$16$ bit data bus size in $%2CS4ADL.8$I/O$memory$ space.
         External bus ready is $%ECS4ADL.7$.
$$IF$CS4ADL.10 || CS4MSKL.10
         SMM region is accessable during $%2CS4ADL.10$$SMI access$ $%2CS4MSKL.10$$and memory access$.
$$END$
$$IFN$CS4ADL.10 &! CS4MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS5:   $%2CS_BEG_END.7$Start$Ending$ address is @@CS5STARTX@.
         Region size is @@CS5LEN@ $%2CS5ADL.8$$K$bytes.
         $%32CS5ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS5MSKL.0$.
         $%2CS5ADL.9$8$16$ bit data bus size in $%2CS5ADL.8$I/O$memory$ space.
         External bus ready is $%ECS5ADL.7$.
$$IF$CS5ADL.10 || CS5MSKL.10
         SMM region is accessable during $%2CS5ADL.10$$SMI access$ $%2CS5MSKL.10$$and memory access$.
$$END$
$$IFN$CS5ADL.10 &! CS5MSKL.10
         SMM region is accessable during SMI access only.
$$END$
  CS6:   $%2CS_BEG_END.1$Start$Ending$ address is @@CS6STARTX@.
         Region size is @@CS6LEN@ $%2CS6ADL.8$$K$bytes.
         $%32CS6ADL.0-4$0$1$2$3$4$5$6$7$8$9$10$11$12$13$14$15$16$17$18$19$20$21$22$23$25$25$26$27$28$29$30$31$ wait states.
         Upper chip select is $%ECS6MSKL.0$.
         $%2CS6ADL.9$8$16$ bit data bus size in $%2CS6ADL.8$I/O$memory$ space.
         External bus ready is $%ECS6ADL.7$.
$$IF$CS6ADL.10 || CS6MSKL.10
         SMM region is accessable during $%2CS6ADL.10$$SMI access$ $%2CS6MSKL.10$$and memory access$.
$$END$
$$IFN$CS6ADL.10 &! CS6MSKL.10
         SMM region is accessable during SMI access only.
$$END$
*/

#include "80386EX.h"
void Init_CSU(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
  _SetEXRegWord(UCSADL, 0x$$UCSADL$);  /* Configure the upper chip select */
  _SetEXRegWord(UCSADH, 0x$$UCSADH$);
  _SetEXRegWord(UCSMSKL, 0x$$UCSMSKL$);
  _SetEXRegWord(UCSMSKH, 0x$$UCSMSKH$);

  _SetEXRegWord(CS0ADL, 0x$$CS0ADL$);  /* Configure chip select 0 */
  _SetEXRegWord(CS0ADH, 0x$$CS0ADH$);
  _SetEXRegWord(CS0MSKL, 0x$$CS0MSKL$);
  _SetEXRegWord(CS0MSKH, 0x$$CS0MSKH$);

  _SetEXRegWord(CS1ADL, 0x$$CS1ADL$);  /* Configure chip select 1 */
  _SetEXRegWord(CS1ADH, 0x$$CS1ADH$);
  _SetEXRegWord(CS1MSKL, 0x$$CS1MSKL$);
  _SetEXRegWord(CS1MSKH, 0x$$CS1MSKH$);

  _SetEXRegWord(CS2ADL, 0x$$CS2ADL$);  /* Configure chip select 2 */
  _SetEXRegWord(CS2ADH, 0x$$CS2ADH$);
  _SetEXRegWord(CS2MSKL, 0x$$CS2MSKL$);
  _SetEXRegWord(CS2MSKH, 0x$$CS2MSKH$);

  _SetEXRegWord(CS3ADL, 0x$$CS3ADL$);  /* Configure chip select 3 */
  _SetEXRegWord(CS3ADH, 0x$$CS3ADH$);
  _SetEXRegWord(CS3MSKL, 0x$$CS3MSKL$);
  _SetEXRegWord(CS3MSKH, 0x$$CS3MSKH$);

  _SetEXRegWord(CS4ADL, 0x$$CS4ADL$);  /* Configure chip select 4 */
  _SetEXRegWord(CS4ADH, 0x$$CS4ADH$);
  _SetEXRegWord(CS4MSKL, 0x$$CS4MSKL$);
  _SetEXRegWord(CS4MSKH, 0x$$CS4MSKH$);

  _SetEXRegWord(CS5ADL, 0x$$CS5ADL$);  /* Configure chip select 5 */
  _SetEXRegWord(CS5ADH, 0x$$CS5ADH$);
  _SetEXRegWord(CS5MSKL, 0x$$CS5MSKL$);
  _SetEXRegWord(CS5MSKH, 0x$$CS5MSKH$);

  _SetEXRegWord(CS6ADL, 0x$$CS6ADL$);  /* Configure chip select 6 */
  _SetEXRegWord(CS6ADH, 0x$$CS6ADH$);
  _SetEXRegWord(CS6MSKL, 0x$$CS6MSKL$);
  _SetEXRegWord(CS6MSKH, 0x$$CS6MSKH$);

$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}
##80C386EX MPLX#
/* 
Pin Multiplex Configuration Routine
(please see Pin Multiplex screen for details)
*/

#include "80386EX.h"
void PinConfig(void)
{
$$IF$ P3CFG.0 && INTCFG.5 &! MCR0.3
   /* If connecting INT9 to the Pin, must configure INTCFG, MCR0 (for INT9),
      and then finally P3CFG in THAT ORDER. */
    _SetEXRegByte(INTCFG,  0x$$INTCFG$);
    _SetEXRegByte(MCR0,    0x$$MCR0$);
$$END$
$$ELSE$
$$IF$ P3CFG.1 && INTCFG.6 &! MCR1.3
   /* If connecting INT8 to the Pin, must configure INTCFG, MCR1 (for INT8),
      and then finally P3CFG in THAT ORDER. */
    _SetEXRegByte(INTCFG,  0x$$INTCFG$);
    _SetEXRegByte(MCR1,    0x$$MCR1$);
$$END$ 
$$END$  
_SetEXRegByte(PINCFG, 0x$$PINCFG$);
_SetEXRegByte(P1CFG, 0x$$P1CFG$);
_SetEXRegByte(P2CFG, 0x$$P2CFG$);
_SetEXRegByte(P3CFG, 0x$$P3CFG$);
}