386exc.cod

mcs51,2051,x86系列MCU

$$IF$ P2DIR.6 && P2LTC.6 &! P2CFG.6
 PIN 6 = Input
$$END$
$$IFN$ P2DIR.6 &! P2CFG.6
 PIN 6 = Output
$$END$
$$IF$ P2DIR.6 &! P2LTC.6 &! P2CFG.6
 PIN 6 = Open Drain
$$END$
$$IF$ P2CFG.7
 PIN 7 = CTS0# Peripheral Pin
$$END$
$$IF$ P2DIR.7 && P2LTC.7 &! P2CFG.7
 PIN 7 = Input
$$END$
$$IFN$ P2DIR.7 &! P2CFG.7
 PIN 7 = Output
$$END$
$$IF$ P2DIR.7 &! P2LTC.7 &! P2CFG.7
 PIN 7 = Open Drain
$$END$
*/

#include "80386EX.h"
void Init_IO2(void)
{
  _SetEXRegByte(P2LTC, 0x$$P2LTC$);
  _SetEXRegByte(P2DIR, 0x$$P2DIR$);
  _SetEXRegByte(P2CFG, 0x$$P2CFG$);
}

##80C386EX IO3#
$$IFN$ REMAPCFG.15
/* ******************************************
   * Must have expanded I/O space enabled   *
   * to initialize this peripheral.  The    *
   * expanded I/O space is enabled only in  *
   * the Enhanced Dos Mode and the NonDos   *
   * Mode.                                  *
   ******************************************
*/
$$END$
/* 
Initialize I/O Port 3 for:
$$IF$ P3CFG.0
 PIN 0 = TMROUT0/INT9 Peripheral Pin
$$END$
$$IF$ P3DIR.0 && P3LTC.0 &! P3CFG.0
 PIN 0 = Input
$$END$
$$IFN$ P3DIR.0 &! P3CFG.0
 PIN 0 = Output
$$END$
$$IF$ P3DIR.0 &! P3LTC.0 &! P3CFG.0
 PIN 0 = Open Drain
$$END$
$$IF$ P3CFG.1
 PIN 1 = TMROUT1/INT8 Peripheral Pin
$$END$
$$IF$ P3DIR.1 && P3LTC.1 &! P3CFG.1
 PIN 1 = Input
$$END$
$$IFN$ P3DIR.1 &! P3CFG.1
 PIN 1 = Output
$$END$
$$IF$ P3DIR.1 &! P3LTC.1 &! P3CFG.1
 PIN 1 = Open Drain
$$END$
$$IF$ P3CFG.2
 PIN 2 = INT0 Peripheral Pin
$$END$
$$IF$ P3DIR.2 && P3LTC.2 &! P3CFG.2
 PIN 2 = Input
$$END$
$$IFN$ P3DIR.2 &! P3CFG.2
 PIN 2 = Output
$$END$
$$IF$ P3DIR.2 &! P3LTC.2 &! P3CFG.2
 PIN 2 = Open Drain
$$END$
$$IF$ P3CFG.3
 PIN 3 = INT1 Peripheral Pin
$$END$
$$IF$ P3DIR.3 && P3LTC.3 &! P3CFG.3
 PIN 3 = Input
$$END$
$$IFN$ P3DIR.3 &! P3CFG.3
 PIN 3 = Output
$$END$
$$IF$ P3DIR.3 &! P3LTC.3 &! P3CFG.3
 PIN 3 = Open Drain
$$END$
$$IF$ P3CFG.4
 PIN 4 = INT2 Peripheral Pin
$$END$
$$IF$ P3DIR.4 && P3LTC.4 &! P3CFG.4
 PIN 4 = Input
$$END$
$$IFN$ P3DIR.4 &! P3CFG.4
 PIN 4 = Output
$$END$
$$IF$ P3DIR.4 &! P3LTC.4 &! P3CFG.4
 PIN 4 = Open Drain
$$END$
$$IF$ P3CFG.5
 PIN 5 = INT3 Peripheral Pin
$$END$
$$IF$ P3DIR.5 && P3LTC.5 &! P3CFG.5
 PIN 5 = Input
$$END$
$$IFN$ P3DIR.5 &! P3CFG.5
 PIN 5 = Output
$$END$
$$IF$ P3DIR.5 &! P3LTC.5 &! P3CFG.5
 PIN 5 = Open Drain
$$END$
$$IF$ P3CFG.6
 PIN 6 = PWRDOWN Peripheral Pin
$$END$
$$IF$ P3DIR.6 && P3LTC.6 &! P3CFG.6
 PIN 6 = Input
$$END$
$$IFN$ P3DIR.6 &! P3CFG.6
 PIN 6 = Output
$$END$
$$IF$ P3DIR.6 &! P3LTC.6 &! P3CFG.6
 PIN 6 = Open Drain
$$END$
$$IF$ P3CFG.7
 PIN 7 = COMCLK Peripheral Pin
$$END$
$$IF$ P3DIR.7 && P3LTC.7 &! P3CFG.7
 PIN 7 = Input
$$END$
$$IFN$ P3DIR.7 &! P3CFG.7
 PIN 7 = Output
$$END$
$$IF$ P3DIR.7 &! P3LTC.7 &! P3CFG.7
 PIN 7 = Open Drain
$$END$
*/

#include "80386EX.h"
void Init_IO3(void)
{
  _SetEXRegByte(P3LTC, 0x$$P3LTC$);
  _SetEXRegByte(P3DIR, 0x$$P3DIR$);
$$IF$ P3CFG.0
   /*See generated code in Pin Multiplex Peripheral screen for TIMER0/INT9 mux setting. */
$$END$
$$ELSE$
$$IF$ P3CFG.1
   /*See generated code in Pin Multiplex Peripheral screen for TIMER1/INT8 mux setting. */
$$END$ 
$$END$  
  _SetEXRegByte(P3CFG, 0x$$P3CFG$);
}

##80C386EX ICU#
/* 
Initialize the Interrupt Control Unit for:
   Slave 8259A is mapped in slot $%2REMAPCFG.4$0$15$.
   Master 8259A is mapped in slot $%2REMAPCFG.3$0$15$.

  Triggering: Master is $%2ICW1M.3$edge$level$ triggered.
              Slave is $%2ICW1S.3$edge$level$ triggered.

  Interrupt type Base: Master is 0$$ICW2M$H.
                       Slave is 0$$ICW2S$H.

  1 slave connected to IR2.
  Special fully nested mode: Master is $%EICW4M.4$.
                             Slave is not allowed.

  Automatic EOI mode: Master is $%EICW4M.1$.
                      Slave is not allowed.

  External interrupt pins used:
$$IFN$ P3CFG.2-5 &! INTCFG.0 &! INTCFG.2-3
                            None
$$END$
$$IF$ P3CFG.2
                            INT0
$$END
$$IF$ P3CFG.3
                            INT1
$$END
$$IF$ P3CFG.4
                            INT2
$$END
$$IF$ P3CFG.5
                            INT3
$$END
$$IF$ INTCFG.0
                            INT4
$$END
$$IF$ INTCFG.1
                            INT5
$$END
$$IF$ INTCFG.2
                            INT6
$$END
$$IF$ INTCFG.3
                            INT7
$$END
*/

#include "80386EX.h"
void Init_ICU(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
  _SetEXRegByte(ICW1S$%2REMAPCFG.4$DOS$$, 0x$$ICW1S$); /* Set slave triggering */
  _SetEXRegByte(ICW2S$%2REMAPCFG.4$DOS$$, 0x$$ICW2S$); /* Set slave base interrupt type */
  _SetEXRegByte(ICW3S$%2REMAPCFG.4$DOS$$, 0x$$ICW3S$); /* Set slave cascade pins */
  _SetEXRegByte(ICW4S$%2REMAPCFG.4$DOS$$, 0x$$ICW4S$); /* Set slave IDs */

  _SetEXRegByte(ICW1M$%2REMAPCFG.3$DOS$$, 0x$$ICW1M$); /* Set master triggering */
  _SetEXRegByte(ICW2M$%2REMAPCFG.3$DOS$$, 0x$$ICW2M$); /* Set master base interrupt type */
  _SetEXRegByte(ICW3M$%2REMAPCFG.3$DOS$$, 0x$$ICW3M$); /* Set master cascade pins */
  _SetEXRegByte(ICW4M$%2REMAPCFG.3$DOS$$, 0x$$ICW4M$); /* Set slave IDs in master */

  _SetEXRegByte(INTCFG, 0x$$INTCFG$); /* Set external interrupt pins */
  _SetEXRegByte(P3CFG, 0x$$P3CFG$); /* Set external interrupt pins */
$$IFN$ REMAPCFG.15

/* Restore I/O space to original condition.*/
  _DisableExtIOMem();
$$END$
}

##80C386EX DMA0#
/* 
Initialize DMA Channel 0 for:
  DMA channel 0 is mapped in slot $%2REMAPCFG.2$0$15$.

$$IF$ DMA0MSK.2
  DMA channel 0 is unsynchronized, responding to software requests only.
  Synchronizing source will be $%6DMACFG.0-2$external (DRQ0)$SIO-0 receiver$SIO-1 transmitter$SSIO transmitter$timer 1$unSynchronized$ if hardware requests are enabled.
$$END$
$$IFN$ DMA0MSK.2
  Synchronizing source is $%6DMACFG.0-2$external (DRQ0)$SIO-0 receiver$SIO-1 transmitter$SSIO transmitter$timer 1$unSynchronized$.
$$END$
  Hardware requests are $%2DMA0MSK.2$enabled$disabled$.
  Operating mode is $%4DMA0MOD1.6-7$demand transfer$single transfer$block$cascade$ mode.
$$IF$ DMACMD1.4
  Priority is configured as rotating priority.
$$END$
$$IFN$ DMACMD1.4
  The priority is set with $%3DMACMD2.2-3$channel 0$channel 1$ external bus master$ lowest.
$$END$  
$$IFN$ DMACFG.1 || DMA0MSK.2
  The source (requester) address 0$$DMA0REQ2/3$:$$DMA0REQ0/1$H.
  Source (requester) addressing is from $%2DMA0MOD2.6$memory$I/O$ space.
  The source (requester) is performing $%2DMA0BSR.6$word$byte$ transfers.
$$IF$ DMA0MOD2.4
  The source (requester) address is held constant.
$$END$
$$IFN$ DMA0MOD2.4 && DMA0MOD2.3 && DMAOVFE.1
  The source (requester) address has all bits decremented.
$$END$
$$IFN$ DMA0MOD2.4 && DMA0MOD2.3 &! DMAOVFE.1
  The source (requester) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA0MOD2.4 &! DMA0MOD2.3 && DMAOVFE.1
  The source (requester) address has all bits incremented.
$$END$
$$IFN$ DMA0MOD2.4 &! DMA0MOD2.3 &! DMAOVFE.1
  The source (requester) address has the low 16 bits incremented.
$$END$
  The destination (target) address 0$$DMA0TAR2/3$:$$DMA0TAR0/1$H.
  Destination (target) addressing is to $%2DMA0MOD2.5$memory$I/O$ space.
  The destination (target) is performing $%2DMA0BSR.4$word$byte$ transfers.
$$IF$ DMA0MOD2.2
  The destination (target) address is held constant.
$$END$
$$IFN$ DMA0MOD2.2 && DMA0MOD1.5 && DMAOVFE.0
  The destination (target) address has all bits decremented.
$$END$
$$IFN$ DMA0MOD2.2 && DMA0MOD1.5 &! DMAOVFE.0
  The destination (target) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA0MOD2.2 &! DMA0MOD1.5 && DMAOVFE.0
  The destination (target) address has all bits incremented.
$$END$
$$IFN$ DMA0MOD2.2 &! DMA0MOD1.5 &! DMAOVFE.0
  The destination (target) address has the low 16 bits incremented.
$$END$
$$END$
$$IF$ DMACFG.1 &! DMA0MSK.2
  The source (target) address 0$$DMA0TAR2/3$:$$DMA0TAR0/1$H.
  Source (target) addressing is from $%2DMA0MOD2.5$memory$I/O$ space.
  The source (target) is performing $%2DMA0BSR.4$word$byte$ transfers.
$$IF$ DMA0MOD2.2
  The source (target) address is held constant.
$$END$
$$IFN$ DMA0MOD2.2 && DMA0MOD1.5 && DMAOVFE.0
  The source (target) address has all bits decremented.
$$END$
$$IFN$ DMA0MOD2.2 && DMA0MOD1.5 &! DMAOVFE.0
  The source (target) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA0MOD2.2 &! DMA0MOD1.5 && DMAOVFE.0
  The source (target) address has all bits incremented.
$$END$
$$IFN$ DMA0MOD2.2 &! DMA0MOD1.5 &! DMAOVFE.0
  The source (target) address has the low 16 bits incremented.
$$END$
  The destination (requester) address 0$$DMA0REQ2/3$:$$DMA0REQ0/1$H.
  Destination (requester) addressing is to $%2DMA0MOD2.6$memory$I/O$ space.
  The destination (requester) is performing $%2DMA0BSR.6$word$byte$ transfers.
$$IF$ DMA0MOD2.4
  The destination (requester) address is held constant.
$$END$
$$IFN$ DMA0MOD2.4 && DMA0MOD2.3 && DMAOVFE.1
  The destination (requester) address has all bits decremented.
$$END$
$$IFN$ DMA0MOD2.4 && DMA0MOD2.3 &! DMAOVFE.1
  The destination (requester) address has the low 16 bits decremented.
$$END$
$$IFN$ DMA0MOD2.4 &! DMA0MOD2.3 && DMAOVFE.1
  The destination (requester) address has all bits incremented.
$$END$
$$IFN$ DMA0MOD2.4 &! DMA0MOD2.3 &! DMAOVFE.1
  The destination (requester) address has the low 16 bits incremented.
$$END$
$$END
$$IFN$ DMA0MOD1.6 |! DMA0MOD1.7
  The transfer type is $%3DMA0MOD1.2-3$verify$write$read$.
$$END$
$$IF$ DMA0MOD1.6 && DMA0MOD1.7
  The transfer type is N/A in cascade mode.
$$END$
  The transfer count is 0$$DMA0BYC2$:$$DMA0BYC0/1$H.
  The sampling configuration is $%4DMACMD2.0-1$DREQ and EOP asynchronous$DREQ synchronous, EOP asynchronous$DREQ asynchronous, EOP synchronous$DREQ and EOP synchronous$.
  The transfer rate is $%2DMA0MOD2.7$1 cycle (fly by)$2 cycles$.
  The channel is $%EDMAGRPMSK.0$.
  Chaining is $%EDMA0CHR.2$.
  Auto-initialization is $%EDMA0MOD1.4$.
  The TC interrupt is $%EDMAIEN.0$.
$$IFN$ PINCFG.3 |! PINCFG.4
  External connections are made to $%4PINCFG.3-4$EOP and DACK$DACK$EOP$$.
$$END$
$$IF$ PINCFG.3 && PINCFG.4
  No external connections are made.
$$END$

Note: Call "Send_DMA0_SW_Req" to initiate a software DMA Request.
*/

#include "80386EX.h"
void Init_DMA0(void)
{
$$IFN$ REMAPCFG.15
/* Enable expanded I/O space for peripheral initialization.*/
  _EnableExtIOMem();

$$END$
  _SetEXRegByte(DMACFG, 0x$$DMACFG$);/* Set the sync. source */
  _SetEXRegByte(DMACMD1, 0x$$DMACMD1$);
  _SetEXRegByte(DMACMD2, 0x$$DMACMD2$);
  _SetEXRegByte(DMAMOD1, 0x$$DMA0MOD1$);