📄 386ex.mpx
字号:
SIGNALBEGIN // Signal 1
2
P3.7
P3CFG.7 0
.
COMCLK
P3CFG.7 1
.
P3CFG.7 1
SIGNALEND
// Start of Timer 1
#
Timer 1
3 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 3
2
TMRGATE1
PXCFG.6 1
.
INT7
PXCFG.6 0
.
PXCFG.6 0
SIGNALEND
SIGNALBEGIN // Signal 2
3
TMROUT1
P3CFG.1 1
INTCFG.6 0
.
INT8
P3CFG.1 1
INTCFG.6 1
MCR1.3 0
.
P3.1
P3CFG.1 0
.
P3CFG.1 0 2 // if P3CFG.1 is 0, init to index 2 (P3.1)
INTCFG.6 0 0 // else if INTCFG.6 is 0, init to index 0 (TMROUT1)
1 // else, init to index 1 (INT8)
SIGNALEND
SIGNALBEGIN // Signal 4
2
TMRCLK1
PXCFG.7 1
.
INT6
PXCFG.7 0
.
PXCFG.7 0
SIGNALEND
// Start of CPU signals
#
CPU Signals
6 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 6
2
LOCK#
P1CFG.5 1
.
P1.5
P1CFG.5 0
.
P1CFG.5 0
SIGNALEND
SIGNALBEGIN // Signal 5
2
HOLD
P1CFG.6 1
.
P1.6
P1CFG.6 0
.
P1CFG.6 0
SIGNALEND
SIGNALBEGIN // Signal 4
2
HLDA
P1CFG.7 1
.
P1.7
P1CFG.7 0
.
P1CFG.7 0
SIGNALEND
SIGNALBEGIN // Signal 3
2
BUSY#
PXCFG.8 0
.
TMRGATE2
PXCFG.8 1
.
PXCFG.8 1
SIGNALEND
SIGNALBEGIN // Signal 2
2
ERROR#
PXCFG.9 0
.
TMR2OUT
PXCFG.9 1
.
PXCFG.9 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
PEREQ
PZCFG.0 0
.
TMRCLK2
PXCFG.0 1
.
PXCFG.0 1
SIGNALEND
// Start of Chip Selects
#
Chip Selects
7 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 7
2
CS0#
P2CFG.0 1
.
P2.0
P2CFG.0 0
.
P2CFG.0 0
SIGNALEND
SIGNALBEGIN // Signal 6
2
CS1#
P2CFG.1 1
.
P2.1
P2CFG.1 0
.
P2CFG.1 0
SIGNALEND
SIGNALBEGIN // Signal 5
2
CS2#
P2CFG.2 1
.
P2.2
P2CFG.2 0
.
P2CFG.2 0
SIGNALEND
SIGNALBEGIN // Signal 4
2
CS3#
P2CFG.3 1
.
P2.3
P2CFG.3 0
.
P2CFG.3 0
SIGNALEND
SIGNALBEGIN // Signal 3
2
CS4#
P2CFG.4 1
.
P2.4
P2CFG.4 0
.
P2CFG.4 0
SIGNALEND
SIGNALBEGIN // Signal 2
2
CS5#
PINCFG.4 1
.
DACK0#
PINCFG.4 0
.
PINCFG.4 0
SIGNALEND
SIGNALBEGIN // Signal 1
2
CS6#
PINCFG.6 0
.
REFRESH#
PINCFG.6 1
.
PINCFG.6 1
SIGNALEND
// Start of Refresh Unit
#
Refresh Unit
1 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 7
2
REFRESH#
PINCFG.6 1
.
CS6#
PINCFG.6 0
.
PINCFG.6 0
SIGNALEND
// Start of Serial Port 1
#
Serial Port 1
8 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 8
2
RXD1
PZCFG.1 0
.
DRQ1
PZCFG.1 1
.
PZCFG.1 1
SIGNALEND
SIGNALBEGIN // Signal 7
2
TXD1
PINCFG.2 1
.
DACK1#
PINCFG.2 0
.
PINCFG.2 0
SIGNALEND
SIGNALBEGIN // Signal 6
2
CTS1#
PINCFG.3 1
.
EOP#
PINCFG.3 0
.
POMCFG.3 0
SIGNALEND
SIGNALBEGIN // Signal 5
2
RTS1#
PINCFG.0 0
.
SSIOTX
PINCFG.0 1
.
PINCFG.6 1
SIGNALEND
SIGNALBEGIN // Signal 4
2
DSR1#
PXCFG.5 0
.
STXCLK
PXCFG.5 1
.
PXCFG.5 1
SIGNALEND
SIGNALBEGIN // Signal 3
2
DTR1#
PINCFG.1 0
.
SRXCLK
PINCFG.1 1
.
PINCFG.1 1
SIGNALEND
SIGNALBEGIN // Signal 2
2
DCD1#
PXCFG.1 0
.
DRQ0
PXCFG.1 1
.
PXCFG.1 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
RI1#
PXCFG.2 0
.
SSIORX
PXCFG.2 1
.
PXCFG.2 1
SIGNALEND
// Start of DMA Channel 1
#
DMA Channel 1
3 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 3
2
DRQ1
PZCFG.1 1
.
RXD1
PZCFG.1 0
.
PZCFG.1 0
SIGNALEND
SIGNALBEGIN // Signal 2
2
DACK1#
PINCFG.2 0
.
TXD1
PINCFG.2 1
.
PINCFG.2 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
EOP#
PINCFG.3 0
.
CTS1#
PINCFG.3 1
.
PINCFG.3 1
SIGNALEND
// Start of I/O Port 2
#
I/O Port 2
8 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 8
2
P2.0
P2CFG.0 0
.
CS0#
P2CFG.0 1
.
P2CFG.0 1
SIGNALEND
SIGNALBEGIN // Signal 7
2
P2.1
P2CFG.1 0
.
CS1#
P2CFG.1 1
.
P2CFG.1 1
SIGNALEND
SIGNALBEGIN // Signal 6
2
P2.2
P2CFG.2 0
.
CS2#
P2CFG.2 1
.
P2CFG.2 1
SIGNALEND
SIGNALBEGIN // Signal 5
2
P2.3
P2CFG.3 0
.
CS3#
P2CFG.3 1
.
P2CFG.3 1
SIGNALEND
SIGNALBEGIN // Signal 4
2
P2.4
P2CFG.4 0
.
CS4#
P2CFG.4 1
.
P2CFG.4 1
SIGNALEND
SIGNALBEGIN // Signal 3
2
P2.5
P2CFG.5 0
.
RXD0
P2CFG.5 1
.
P2CFG.5 1
SIGNALEND
SIGNALBEGIN // Signal 2
2
P2.6
P2CFG.6 0
.
TXD0
P2CFG.6 1
.
P2CFG.6 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
P2.7
P2CFG.7 0
.
CTS0#
P2CFG.7 1
.
P2CFG.7 1
SIGNALEND
// Start of Timer 0
#
Timer 0
3 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 3
2
TMRGATE0
PXCFG.4 1
.
INT5
PXCFG.4 0
.
PXCFG.4 0
SIGNALEND
SIGNALBEGIN // Signal 2
3
TMROUT0
P3CFG.0 1
INTCFG.5 0
.
INT9
P3CFG.0 1
INTCFG.5 1
MCR0.3 0
.
P3.0
P3CFG.0 0
.
P3CFG.0 0 2 // if P3CFG.0 is 0, init to index 2 (P3.0)
INTCFG.5 0 0 // else if INTCFG.5 is 0, init to index 0 (TMROUT0)
1 // else, init to index 1 (INT9)
SIGNALEND
SIGNALBEGIN // Signal 1
2
TMRCLK0
PXCFG.0 1
.
INT4
PXCFG.0 0
.
PXCFG.0 0
SIGNALEND
// Start of Timer 2
#
Timer 2
3 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 3
2
TMRGATE2
PXCFG.8 1
.
BUSY#
PXCFG.8 0
.
PXCFG.8 0
SIGNALEND
SIGNALBEGIN // Signal 2
2
TMR2OUT
PINCFG.5 1
.
ERROR#
PINCFG.5 0
.
PINCFG.5 0
SIGNALEND
SIGNALBEGIN // Signal 1
2
TMRCLK2
PZCFG.0 1
.
PEREQ
PZCFG.0 0
.
PZCFG.0 0
SIGNALEND
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