📄 386ex.mpx
字号:
//
// 386 Pin multi-plexing Data-file.
//
// Search for '#' or '// Start of' to find the beginning of each peripherals signal definitions.
//
// See MPLX.DOC in the ApBuilder documents directory for help on the format and syntax of this file.
//
// Special Note: PXCFG and PZCFG ( non-existant SFRs ) used where selection desired to be shown, but no
// code actually needed (operation depends on user hookup, and no actual mux exists)
//
Intel 386(TM) EX Pin Multiplexing // Name of screen title
16 // Number of Peripherals
// Start of Clock/Pwr Mgmt here.
#
Clock/Pwr Mgmt // Name of first peripheral
2 // Number of Muxed signals for this peripheral
SIGNALBEGIN // start of THIRD signal definition (remember, opposite order)
2 // Signal muxed 3 ways.
PWRDOWN // Name of first selection
P3CFG.6 1
. // end of operations list.
P3.6 // Name of second selection for signal
P3CFG.6 0
.
P3CFG.6 0 // If P3CFG.6 is set, use PWRDOWN
SIGNALEND
SIGNALBEGIN // .Start SECOND signal definition
2 // Signal muxed 3 ways.
COMCLK // Name of first selection
P3CFG.7 1
. // end of operations list.
P3.7 // Name of second selection for signal
P3CFG.7 0
.
P3CFG.7 0 // If P3CFG.7 is set, use COMCLK
SIGNALEND
// Start of Interrupt Unit configuration here..
#
Interrupt Unit // Name of second peripheral
10 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 10
2
INT0
P3CFG.2 1
.
P3.2
P3CFG.2 0
.
P3CFG.2 0
SIGNALEND
SIGNALBEGIN // Signal 9
2
INT1
P3CFG.3 1
.
P3.3
P3CFG.3 0
.
P3CFG.3 0
SIGNALEND
SIGNALBEGIN // Signal 8
2
INT2
P3CFG.4 1
.
P3.4
P3CFG.4 0
.
P3CFG.4 0
SIGNALEND
SIGNALBEGIN // Signal 7
2
INT3
P3CFG.5 1
.
P3.5
P3CFG.5 0
.
P3CFG.5 0
SIGNALEND
SIGNALBEGIN // Signal 6
2
INT4
PXCFG.0 0
.
TMRCLK0
PXCFG.0 1
.
PXCFG.0 1
SIGNALEND
SIGNALBEGIN // Signal 5
2
INT5
PXCFG.4 0
.
TMRGATE0
PXCFG.4 1
.
PXCFG.4 1
SIGNALEND
SIGNALBEGIN // Signal 4
2
INT6
PXCFG.7 0
.
TMRCLK1
PXCFG.7 1
.
PXCFG.7 1
SIGNALEND
SIGNALBEGIN // Signal 3
2
INT7
PXCFG.6 0
.
TMRGATE1
PXCFG.6 1
.
PXCFG.6 1
SIGNALEND
SIGNALBEGIN // Signal 2
3
INT8
P3CFG.1 1
INTCFG.6 1
MCR1.3 0
.
TMROUT1
P3CFG.1 1
INTCFG.6 0
.
P3.1
P3CFG.1 0
.
P3CFG.1 0 2 // if P3CFG.1 is 0, init to index 2 (P3.1)
INTCFG.6 0 1 // else if INTCFG.6 is 0, init to index 1 (TMROUT1)
0 // else, init to index 0 (INT8)
SIGNALEND
SIGNALBEGIN // Signal 1
3
INT9
P3CFG.0 1
INTCFG.5 1
MCR0.3 0
.
TMROUT0
P3CFG.0 1
INTCFG.5 0
.
P3.0
P3CFG.0 0
.
P3CFG.0 0 2 // if P3CFG.0 is 0, init to index 2 (P3.0)
INTCFG.5 0 1 // else if INTCFG.5 is 0, init to index 1 (TMROUT0)
0 // else, init to index 0 (INT9)
SIGNALEND
// Start of Synch. Serial Port
#
Sync. Serial Port
4 // Number of Muxed signals for this peripheral
SIGNALBEGIN
2
SSIORX
PXCFG.2 1
.
RI1#
PXCFG.2 0
.
PXCFG.2 0
SIGNALEND
SIGNALBEGIN
2
SSIOTX
PXCFG.3 1
.
RTS1#
PXCFG.3 0
.
PXCFG.3 0
SIGNALEND
SIGNALBEGIN
2
STXCLK
PXCFG.5 1
.
DSR1#
PXCFG.5 0
.
PXCFG.5 0
SIGNALEND
SIGNALBEGIN
2
SRXCLK
PINCFG.1 1
.
DTR1#
PINCFG.1 0
.
PINCFG.0 0
SIGNALEND
// Start of Serial Port 0
#
Serial Port 0
8 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 8
2
RXD0
P2CFG.5 1
.
P2.5
P2CFG.5 0
.
P2CFG.5 0
SIGNALEND
SIGNALBEGIN // Signal 7
2
TXD0
P2CFG.6 1
.
P2.6
P2CFG.6 0
.
P2CFG.6 0
SIGNALEND
SIGNALBEGIN // Signal 6
2
CTS0#
P2CFG.7 1
.
P2.7
P2CFG.7 0
.
P2CFG.7 0
SIGNALEND
SIGNALBEGIN // Signal 5
2
RTS0#
P1CFG.1 1
.
P1.1
P1CFG.1 0
.
P1CFG.1 0
SIGNALEND
SIGNALBEGIN // Signal 4
2
DSR0#
P1CFG.3 1
.
P1.3
P1CFG.3 0
.
P1CFG.3 0
SIGNALEND
SIGNALBEGIN // Signal 3
2
DTR0#
P1CFG.2 1
.
P1.2
P1CFG.2 0
.
P1CFG.2 0
SIGNALEND
SIGNALBEGIN // Signal 2
2
DCD0#
P1CFG.0 1
.
P1.0
P1CFG.0 0
.
P1CFG.0 0
SIGNALEND
SIGNALBEGIN // Signal 1
2
RI0#
P1CFG.4 1
.
P1.4
P1CFG.4 0
.
P1CFG.4 0
SIGNALEND
// Start of DMA Channel 0
#
DMA Channel 0
3 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 3
2
DRQ0
PXCFG.1 1
.
DCD1#
PXCFG.1 0
.
PXCFG.1 0
SIGNALEND
SIGNALBEGIN // Signal 2
2
DACK0#
PINCFG.4 0
.
CS5#
PINCFG.4 1
.
PINCFG.4 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
EOP#
PINCFG.3 0
.
CTS1#
PINCFG.3 1
.
PINCFG.3 1
SIGNALEND
// Start of I/O Port 1
#
I/O Port 1
8 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 8
2
P1.0
P1CFG.0 0
.
DCD0#
P1CFG.0 1
.
P1CFG.0 1
SIGNALEND
SIGNALBEGIN // Signal 7
2
P1.1
P1CFG.1 0
.
RTS0#
P1CFG.1 1
.
P1CFG.1 1
SIGNALEND
SIGNALBEGIN // Signal 6
2
P1.2
P1CFG.2 0
.
DTR0#
P1CFG.2 1
.
P1CFG.2 1
SIGNALEND
SIGNALBEGIN // Signal 5
2
P1.3
P1CFG.3 0
.
DSR0#
P1CFG.3 1
.
P1CFG.3 1
SIGNALEND
SIGNALBEGIN // Signal 4
2
P1.4
P1CFG.4 0
.
RI0#
P1CFG.4 1
.
P1CFG.4 1
SIGNALEND
SIGNALBEGIN // Signal 3
2
P1.5
P1CFG.5 0
.
LOCK#
P1CFG.5 1
.
P1CFG.5 1
SIGNALEND
SIGNALBEGIN // Signal 2
2
P1.6
P1CFG.6 0
.
HOLD
P1CFG.6 1
.
P1CFG.6 1
SIGNALEND
SIGNALBEGIN // Signal 1
2
P1.7
P1CFG.7 0
.
HLDA
P1CFG.7 1
.
P1CFG.7 1
SIGNALEND
// Start of I/O Port 3
#
I/O Port 3
8 // Number of Muxed signals for this peripheral
SIGNALBEGIN // Signal 8
3
P3.0
P3CFG.0 0
.
INT9
P3CFG.0 1
INTCFG.5 1
MCR0.3 0
.
TMROUT0
P3CFG.0 1
INTCFG.5 0
.
P3CFG.0 0 0 // if P3CFG.0 is 0, init to index 0 (P3.0)
INTCFG.5 0 2 // else if INTCFG.5 is 0, init to index 2 (TMROUT0)
1 // else, init to index 1 (INT9)
SIGNALEND
SIGNALBEGIN // Signal 7
3
P3.1
P3CFG.1 0
.
INT8
P3CFG.1 1
INTCFG.6 1
MCR1.3 0
.
TMROUT1
P3CFG.1 1
INTCFG.6 0
.
P3CFG.1 0 0 // if P3CFG.1 is 0, init to index 0 (P3.1)
INTCFG.6 0 2 // else if INTCFG.6 is 0, init to index 2 (TMROUT1)
1 // else, init to index 1 (INT8)
SIGNALEND
SIGNALBEGIN // Signal 6
2
P3.2
P3CFG.2 0
.
INT0
P3CFG.2 1
.
P3CFG.2 1
SIGNALEND
SIGNALBEGIN // Signal 5
2
P3.3
P3CFG.3 0
.
INT1
P3CFG.3 1
.
P3CFG.3 1
SIGNALEND
SIGNALBEGIN // Signal 4
2
P3.4
P3CFG.4 0
.
INT2
P3CFG.4 1
.
P3CFG.4 1
SIGNALEND
SIGNALBEGIN // Signal 3
2
P3.5
P3CFG.5 0
.
INT3
P3CFG.5 1
.
P3CFG.5 1
SIGNALEND
SIGNALBEGIN // Signal 2
2
P3.6
P3CFG.6 0
.
PWRDOWN
P3CFG.6 1
.
P3CFG.6 1
SIGNALEND
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -