pe386ex.rd1

mcs51,2051,x86系列MCU

#Timer0 80C386EX 121#
#Timer1 80C386EX 121#
#Timer2 80C386EX 121#
This option selects the external timer clock (TMRCLK) to be the clocking source for the timer counter. The counters can handle input frequencies up to 1/2 the processor clock. 
#Timer0 80C386EX 130#
#Timer1 80C386EX 130#
#Timer2 80C386EX 130#
This option selects the GATE signal's source to be VCC. 
#Timer0 80C386EX 131#
#Timer1 80C386EX 131#
#Timer2 80C386EX 131#
This option selects the GATE signal's source to be the external timer gate (TMRGATE) pin. 
#Timer0 80C386EX 132#
#Timer1 80C386EX 132#
#Timer2 80C386EX 132#
Software GATEn Enable.
0 = Connects GATEn to either VCC pin or the TMRGATEn pin.
1 = Enables GT2CON, GT1CON, and GT0CON to control the
    connections to GATE2, GATE1, and GATE0 respectively.
#Timer0 80C386EX 150#
#Timer1 80C386EX 150#
#Timer2 80C386EX 150#
#Timer0 80C386EX 151#
#Timer1 80C386EX 151#
#Timer2 80C386EX 151#
Determine whether to enable or disable the external timer output. 

Enabling this option connects the OUT signal to the external timer clock output (TMROUT) pin. 
#RCU 80C386EX 110#
Set this to enable the Refresh Control Unit.

The Refresh Control Unit simplifies dynamic memory controller design by issuing dummy read cycles at specified intervals. 
#RCU 80C386EX 111#
Set this to disable the Refresh Control Unit. 
#RCU 80C386EX 100#
Specify the value of the Refresh Base Address Register. (RFSBAD)

Use RFSBAD to set up the memory region that needs refreshing. The value written to this register forms the upper bits of the refresh address. Twelve-bit mapping places the refresh address at any 8Kbyte boundary within the 64Mbyte address space. 
#RCU 80C386EX 120#
Specify the required DRAM refresh period (microseconds) for one row. (The time required to refresh one row in the DRAM device.)
#RCU 80C386EX 150#
#RCU 80C386EX 151#
Determine which signal to connect to the package pin, REFRESH# or CS6#. The REFRESH# signal  is associated with the Refresh Control Unit and the CS6# signal is associated with the Chip-Select Unit. 
#RCU 80C386EX 30022#
Specify the frequency of the external clock being provided as an input signal to CLK2. This signal will in turn provide the fundamental timing for the processor at 1/2 the input frequency. i.e. An input signal to CLK2 of 50MHz would provide a processor CLK of 25 MHz. 

(NOTE: The CPU Frequency can also be set in the Clock or Power Management Units. If the frequency is changed in the RCU Unit, it will affect all other units which use this clocking signal.)
#WDT 80C386EX 100#
Determine the function of the Watchdog Timer Unit.

Software Watchdog Timer Mode: System software must periodically reload the down-counter with a reload value. Note: After reset, the WDT defaults to general-purpose timer mode and will time out after 64K clock cycles unless you intervene. 
#WDT 80C386EX 101#
Determine the function of the Watchdog Timer Unit.

Disable WDT: If your system has no need for the WDT, this option will disable the unit. The clock to the WDT is stopped so the WDT consumes minimal power, but the unit can be re-enabled at any time. 
#WDT 80C386EX 102#
Determine the function of the Watchdog Timer Unit.

General Purpose Timer Mode: Default mode after reset. At reset, the down-counter begins decrementing, starting at 0000FFFFH (the initial values of the reload and count registers), and the WDT will time out after 64K clock cycles unless you intervene. During the clock cycle immediately after the down-counter reaches zero, this mode reloads the down-counter with the contents of the reload registers. 
#WDT 80C386EX 103#
Determine the function of the Watchdog Timer Unit.

Bus Monitor Mode: ADS# reloads and starts the down-counter and READY# stops it. The programmed reload value should be slightly longer than the longest bus cycle expected. Changing the reload value and the enabling or disabling of this mode can be done at any time. 
#WDT 80C386EX 201#
Specify the value of the reload registers which are used  to program the down-counter of the Watchdog Timer. 
#Clock 80C386EX 30022#
#PM 80C386EX 30022#
Specify the frequency of the external clock being provided as an input signal to CLK2. This signal will in turn provide the fundamental timing for the processor at 1/2 the input frequency. i.e. An input signal to CLK2 of 50MHz would provide a processor CLK of 25 MHz. 
#Clock 80C386EX 110#
#PM 80C386EX 110#
Specify the desired prescaled clock (PSCLK) frequency. The maximum PSCLK frequency is the internal clock frequency divided by 2 (CLK2/4) and the minimum is the internal clock frequency divided by 513 (CLK2/1026). 

The SSIO and Timer/Counters may be programmed to use the PSCLK. 
#Clock 80C386EX 141#
#PM 80C386EX 141#
Determine which, if any, power conservation mode to enable.

Powerdown Mode: Freezes both the core and peripheral clocks. Powerdown mode reduces power consumption to leakage current (microamps). 
#Clock 80C386EX 1000#
#PM 80C386EX 1000#
Watch Dog Timer Ready:
0 = An external READY must be generated to terminate the cycle when the WDT times out in Bus Monitor Mode.
1 = Internal logic generates READY# to terminate the cycle when the WDT times out in Bus Monitor Mode.
#Clock 80C386EX 1001#
#PM 80C386EX 1001#
Halt/Shutdown Ready:
0 = An external ready must be generated to terminate a HALT/Shutdown cycle.
1 = Internal logic generates READY# to terminate a HALT/Shutdown cycle.
#Clock 80C386EX 142#
#PM 80C386EX 142#
Determine which, if any, power conservation mode to enable.

Idle Mode: Freezes the core clocks but leaves the peripheral clocks running. Idle mode can reduce power consumption by about half, depending on peripheral usage. 
#Clock 80C386EX 140#
#PM 80C386EX 140#
Determine which, if any, power conservation mode to enable.

None: No power conservation mode will be used. 
#DMA0 80C386EX 122#
#DMA1 80C386EX 122#
Specify the Requester Address: The memory or I/O location in which the requester can be found.
#DMA0 80C386EX 142#
#DMA1 80C386EX 142#
Specify the Target Address: The memory or I/O location in which the target can be found.
#DMA0 80C386EX 154#
#DMA1 80C386EX 154#
Specify the transfer count. This determines the number of data transfers that make up a buffer transfer.
#DMA0 80C386EX 175#
Determine which of the four possible hardware sources to connect to channel 0's request input (DRQ0).

DRQ0 pin (external peripheral).
SIO channel 0's receive buffer full signal (RBF).
SIO channel 1's transmit buffer empty signal (TBE)
SSIO transmit holding buffer empty signal (THBE).
TCU counter 1's output signal (OUT1).
#DMA1 80C386EX 175#
Determine which of the four possible hardware sources to connect to channel 1's request input (DRQ1).

DRQ1 pin (external peripheral).
SIO channel 1's receive buffer full signal (RBF).
SIO channel 0's transmit buffer empty signal (TBE)
SSIO receive holding buffer full signal (RHBF).
TCU counter 2's output signal (OUT2).
#DMA0 80C386EX 180#
Setting this option masks (disables) channel 0's hardware requests.  When set, channel 0 can only receive software requests.
#DMA1 80C386EX 180#
Setting this option masks (disables) channel 1's hardware requests.  When set, channel 1 can only receive software requests.
#DMA0 80C386EX 162#
#DMA1 80C386EX 162#
Demand Data Transfer Mode: The channel continues to transfer data while the channel request signal (DRQ) is held active. When the request signal goes inactive, the channel suspends the buffer transfer. 
*** Compatible with ALL buffer-transfer modes. 
NOTE:  because you cannot deactivate the internal channel request signal before the end of a buffer transfer, you cannot use software requests with the demand data-transfer mode.
#DMA0 80C386EX 160#
#DMA1 80C386EX 160#
Single Data Transfer Mode: The channel gives up bus control after every data transfer and must regain bus control (through priority arbitration) before the next data transfer. Therefore, a channel request is required for every data transfer within a buffer transfer. 
*** Compatible will ALL buffer-transfer modes.
#DMA0 80C386EX 161#
#DMA1 80C386EX 161#
Block Data Transfer Mode: A channel request causes the entire buffer of data to be transferred.
*** Compatible with single and autoinitialize buffer-transfer modes, NOT with chaining buffer-transfer mode.
#DMA0 80C386EX 163#
#DMA1 80C386EX 163#
Cascade Data Transfer Mode: Allows an external 8237A or another DMA-type device to gain bus control. A cascaded device requests bus control by holding the request input DRQ active. Once granted bus control, it remains the bus master until it relinquishes the bus control. 
#DMA0 80C386EX 169#
#DMA1 80C386EX 169#
Determine which bus control priority the DMA channel will use.

Refresh requests always have the highest priority, but the priority structure of the other three requests (two DMA channels and an external device) is configurable. Although configurable, the relative priority structure always remains: DMA0, DMA1, External Bus Master. 

Rotating: A requester is automatically assigned the lowest priority level after it gains bus control. This allows requesting devices to share the system more evenly.
 
Channel 0 Lowest: Channel 0 is assigned the lowest priority level.
(DMA1, Ext. Bus Mtr., DMA0)

Channel 1 Lowest: Channel 1 is assigned the lowest priority level. 
(Ext. Bus Mtr., DMA0, DMA1)

External Bus Master Lowest: The External Bus Master is assigned the lowest priority level. (DMA0, DMA1, Ext. Bus Mtr.) 
#DMA0 80C386EX 127#
#DMA1 80C386EX 127#
Selecting this option causes the requester address to be incremented after each data transfer in a buffer transfer.
#DMA0 80C386EX 128#
#DMA1 80C386EX 128#
Selecting this option causes the requester address to be decremented after each data transfer in a buffer transfer.
#DMA0 80C386EX 129#
#DMA1 80C386EX 129#
Selecting this option causes the requester address to remain constant during a buffer transfer. 
#DMA0 80C386EX 131#
#DMA1 80C386EX 131#
Selecting this option causes the lowest 16 bits of the requester address to be incremented/decremented.
#DMA0 80C386EX 132#
#DMA1 80C386EX 132#
Selecting this option causes all of the requester address to be incremented/decremented.
#DMA0 80C386EX 147#
#DMA1 80C386EX 147#
Selecting this option causes the target address to be incremented after each data transfer in a buffer transfer.
#DMA0 80C386EX 148#
#DMA1 80C386EX 148#
Selecting this option causes the target address to be decremented after each data transfer in a buffer transfer.
#DMA0 80C386EX 149#
#DMA1 80C386EX 149#
Selecting this option causes the target address to remain constant during a buffer transfer. 
#DMA0 80C386EX 151#
#DMA1 80C386EX 151#
Selecting this option causes the lowest 16 bits of the target address and byte count to be incremented/decremented.
#DMA0 80C386EX 152#
#DMA1 80C386EX 152#
Selecting this option causes all of the target address and byte count to be incremented/decremented.
#DMA0 80C386EX 177#
#DMA1 80C386EX 177#
Selecting this option causes the DMA to sample the channel request (DRQ) inputs asynchronously:   the DMA samples the inputs at the beginning of every state of requester access, then waits until the end of the state to act on the input.
#DMA0 80C386EX 178#
#DMA1 80C386EX 178#
Selecting this option causes the DMA to sample the channel request (DRQ) inputs synchronously:   the DMA samples the inputs at the end of the last state of every data transfer.
#DMA0 80C386EX 190#
#DMA1 80C386EX 190#
Selecting this option causes the DMA to sample the end-of-process (EOP#) input asynchronously:  the channel samples the input at the beginning of every state of requester access, then waits until the end of the state to act on the input.
#DMA0 80C386EX 191#
#DMA1 80C386EX 191#
Selecting this option causes the DMA to sample the end-of-process (EOP#) input synchronously:  the channel samples EOP# at the end of the last state of every data transfer.
#DMA0 80C386EX 166#
#DMA1 80C386EX 166#
Autoinitialize Buffer-Transfer Mode: The DMA automatically reloads the channel with the original transfer information when the current buffer transfer completes. Useful when it is necessary to transfer a fixed amount of data between the same locations multiple times. 
#DMA0 80C386EX 167#
#DMA1 80C386EX 167#
Chaining Buffer-Transfer Mode: The DMA automatically reprograms the channel after the current buffer transfer is complete. In this mode, the channel is reprogrammed with new transfer information. Useful when data needs to be transferred between multiple requesters and targets. 
#DMA0 80C386EX 165#
#DMA1 80C386EX 165#
Single Buffer-Transfer Mode: The DMA transfers a channel's buffer only once. When the entire buffer of data has been transferred, the channel becomes idle and must be reprogrammed before it can perform another buffer transfer. Useful when the exact amount of data to be transferred is known and there will be time to reprogram the channel.
#DMA0 80C386EX 193#
#DMA1 80C386EX 193#
Setting this option connects the channel's transfer complete (TC) signal to the interrupt control unit's DMAINT input.
#DMA0 80C386EX 121#
#DMA1 80C386EX 121#
Determine the Requester's device type. 

Memory: the requester is in memory space.

I/O (internal):  the requester is in internal I/O space.

I/O (external):  the requester is in external I/O space (the device monitors bus cycle signals to determine when to access the data bus).
#DMA0 80C386EX 141#
#DMA1 80C386EX 141#
Determine the Target's device type. 

Memory: the target is in memory space.

I/O (internal):  the target is in internal I/O space.

I/O (external):  the target is in external I/O space (the device monitors bus cycle signals to determine when to access the data bus). 
#DMA0 80C386EX 124#
#DMA1 80C386EX 124#
Selecting this option specifies an 8-bit data bus width for the requester.
#DMA0 80C386EX 125#
#DMA1 80C386EX 125#
Selecting this option specifies a 16-bit data bus width for the requester.
#DMA0 80C386EX 144#
#DMA1 80C386EX 144#
Selecting this option specifies an 8-bit data bus width for the target.
#DMA0 80C386EX 145#
#DMA1 80C386EX 145#
Selecting this option specifies a 16-bit data bus width for the target.
#DMA0 80C386EX 157#
#DMA1 80C386EX 157#
Determine the transfer direction. 

Read: Data is transferred from the target to the requester. 
#DMA0 80C386EX 158#
#DMA1 80C386EX 158#
Determine the transfer direction. 

Write: Data is transferred from the requester to the target.
#DMA0 80C386EX 156#
#DMA1 80C386EX 156#
Determine the transfer direction. 

Verify: The target it read; nothing is written. (Used for testing.) 
#DMA0 80C386EX 170#
#DMA1 80C386EX 170#
Determine which bus cycle option to use for data transfers: 1-cycle (fly-by) or 2-cycle.

Fly-by (One-cycle): Allows data to be transferred in one bus cycle. Requires that the requester be in external I/O and the target be in memory. 
#DMA0 80C386EX 171#
#DMA1 80C386EX 171#
Determine which bus cycle option to use for data transfers: 1-cycle (fly-by) or 2-cycle.

Two-cycle: Allows data to be transferred between any combination of memory and I/O through the use of a four-byte temporary buffer. The amount of data and the data path widths determine the number of bus cycles required to transfer data. 
#DMA0 80C386EX 185#
Set this bit to enable the channel's DMA acknowledge signal (DACK#) at the device pin. Clear it to disable the DACK# signal at the device pin. Enable the DACK# signal only if the external request signal (DRQ) is being used. (This bit can not be set if the CS5# signal from the Chip-Select Unit is enabled as they are both multiplexed to the same pin.) 
#DMA1 80C386EX 185#
Set this bit to enable the channel's DMA acknowledge signal (DACK#) at the device pin. Clear it to disable the DACK# signal at the device pin. Enable the DACK# signal only if the external request signal (DRQ) is being used. (This bit can not be set if the TXD1 signal from the Asynchronous Serial Channel 1 is enabled as they are both multiplexed to the same pin.) 
#DMA0 80C386EX 186#
Setting this option masks DMA channel 0's acknowledge (DACK0#) signal.  This option is useful when channel 0's request (DRQ0) input is connected to an internal peripheral.
#DMA1 80C386EX 186#
Setting this option masks DMA channel 1's acknowledge (DACK1#) signal.  This option is useful when channel 1's request (DRQ1) input is connected to an internal peripheral.
#DMA0 80C386EX 188#
#DMA1 80C386EX 188#
Determine which signal to connect to the package pin, EOP# or CTS1#.  Set this bit to enable the channel's EOP, End of Process, signal at the device pin. Clear this bit to disable the signal at the device pin. (The EOP# signal is associated with the DMA and the CTS1# signal is associated with the Asynchronous Serial Channel 1.)
#Serial0 80C386EX 110#
#Serial1 80C386EX 110#
Select the number of data bits (5, 6, 7 or 8) in each transmitted or received serial character. 
#Serial0 80C386EX 130#
#Serial1 80C386EX 130#
Determine the type of parity the control logic produces during transmission or checks during reception.

Options: Odd, Even, Mark (Forced parity, bit = 1), Zero (Forced parity, bit = 0), or None (Parity disabled)
#Serial0 80C386EX 140#
#Serial1 80C386EX 140#
Determine which interrupt signals will be enabled. To enable, check the interrupt source, and to disable, clear it.

Receive Buffer Full Interrupt Enable: An interrupt is sent after it transfers a received character from the receive shift register to the receive buffer register. 
#Serial0 80C386EX 141#
#Serial1 80C386EX 141#
Determine which interrupt signals will be enabled. To enable, check the interrupt source, and to disable, clear it.

Transmit Buffer Empty Interrupt Enable: An interrupt is sent when the transmit shift register and transmit buffer register are both empty.