pe386ex.rd1

mcs51,2051,x86系列MCU

#Sync 80C386EX 100#
Determine whether the transmitter will operate in master or slave mode.

Master mode: The internal baud-rate generator controls the serial communications by clocking the internal transmitter. 
#Sync 80C386EX 101#
Determine whether the transmitter will operate in master or slave mode.

Slave Mode: An external master device controls the serial communications by clocking the internal transmitter via the STXCLK pin. 
#Sync 80C386EX 110#
Check to enable the Transmitter; clear to disable. 

When the transmitter is enabled, the contents of the transmitter buffer are immediately transferred to the shift register. In master mode, the baud-rate generator must be programmed and enabled prior to enabling the transmitter. In slave mode, the transmitter must be enabled prior to the application of an external clock. 
#Sync 80C386EX 111#
Check to enable the Transmitter Interrupt; clear to disable.

Enabling the Transmitter Interrupt connects the transmit buffer empty (internal) signal to the interrupt control and DMA units. This allows the use of either an interrupt service routine or a DMA transfer to load the new data in the transmit holding buffer. 
#Sync 80C386EX 120#
Determine whether the receiver will operate in master or slave mode.

Master mode: The internal baud-rate generator controls the serial communications by clocking the internal receiver. 
#Sync 80C386EX 121#
Determine whether the receiver will operate in master or slave mode.

Slave Mode: An external master device controls the serial communications by clocking the internal receiver via the SRXCLK. 
#Sync 80C386EX 130#
Check to enable the Receiver; clear to disable. 

When the receiver is enabled, the shift register shifts data in via the SSIORX pin. If the receiver is enabled, it transfers the contents of the shift register to the receive buffer each time the shift register finishes shifting its current contents. 
#Sync 80C386EX 131#
Check to enable the Receiver Interrupt; clear to disable. 

Enabling the Receiver Interrupt connects the receiver buffer full (internal) signal to the interrupt control and DMA units. This allows the use of either an interrupt service routine or a DMA transfer to read data from the receive holding buffer. 
#Sync 80C386EX 140#
Specify the desired baud rate. NOTE: The baud rate is a function of the input clock frequency and a 9-bit divider (real number) and therefore it may not be possible to achieve the exact baud rate desired. 
#Sync 80C386EX 152#
This option selects the internal serial clock (SERCLK) as the clocking source for the baud-rate generator. This internal signal has a frequency of the processor's input clock, CLK2, divided by four. 
#Sync 80C386EX 153#
This option selects the internal prescaled clock (PSCLK) as the clocking source for the baud-rate generator. This internal signal can have a maximum frequency of CLK2/4 and a minimum frequency of CLK2/1026. It is set in the Clock Unit or Power Management Unit. 
#IO1 80C386EX 100#
#IO2 80C386EX 100#
#IO3 80C386EX 100#
#IO1 80C386EX 110#
#IO2 80C386EX 110#
#IO3 80C386EX 110#
#IO1 80C386EX 120#
#IO2 80C386EX 120#
#IO3 80C386EX 120#
#IO1 80C386EX 130#
#IO2 80C386EX 130#
#IO3 80C386EX 130#
#IO1 80C386EX 140#
#IO2 80C386EX 140#
#IO3 80C386EX 140#
#IO1 80C386EX 150#
#IO2 80C386EX 150#
#IO3 80C386EX 150#
#IO1 80C386EX 160#
#IO2 80C386EX 160#
#IO3 80C386EX 160#
#IO1 80C386EX 170#
#IO2 80C386EX 170#
#IO3 80C386EX 170#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in I/O mode as a  high-impedance input. 
#IO1 80C386EX 101#
#IO2 80C386EX 101#
#IO3 80C386EX 101#
#IO1 80C386EX 111#
#IO2 80C386EX 111#
#IO3 80C386EX 111#
#IO1 80C386EX 121#
#IO2 80C386EX 121#
#IO3 80C386EX 121#
#IO1 80C386EX 131#
#IO2 80C386EX 131#
#IO3 80C386EX 131#
#IO1 80C386EX 141#
#IO2 80C386EX 141#
#IO3 80C386EX 141#
#IO1 80C386EX 151#
#IO2 80C386EX 151#
#IO3 80C386EX 151#
#IO1 80C386EX 161#
#IO2 80C386EX 161#
#IO3 80C386EX 161#
#IO1 80C386EX 171#
#IO2 80C386EX 171#
#IO3 80C386EX 171#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in I/O mode as a  complementary output. 
#IO1 80C386EX 102#
#IO2 80C386EX 102#
#IO3 80C386EX 102#
#IO1 80C386EX 112#
#IO2 80C386EX 112#
#IO3 80C386EX 112#
#IO1 80C386EX 122#
#IO2 80C386EX 122#
#IO3 80C386EX 122#
#IO1 80C386EX 132#
#IO2 80C386EX 132#
#IO3 80C386EX 132#
#IO1 80C386EX 142#
#IO2 80C386EX 142#
#IO3 80C386EX 142#
#IO1 80C386EX 152#
#IO2 80C386EX 152#
#IO3 80C386EX 152#
#IO1 80C386EX 162#
#IO2 80C386EX 162#
#IO3 80C386EX 162#
#IO1 80C386EX 172#
#IO2 80C386EX 172#
#IO3 80C386EX 172#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in I/O mode as an open-drain output.       NOTE: This requires an external pull-up. 
#IO1 80C386EX 103#
#IO1 80C386EX 113#
#IO1 80C386EX 123#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, the Bus Interface Unit, controls the pin. 
#IO1 80C386EX 173#
#IO1 80C386EX 163#
#IO1 80C386EX 153#
#IO1 80C386EX 143#
#IO1 80C386EX 133#
#IO2 80C386EX 123#
#IO2 80C386EX 113#
#IO2 80C386EX 103#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, the Serial I/O Unit0, controls the pin. 
#IO3 80C386EX 103#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripherals, the Serial I/O Unit0 and Unit1, control the pin. 
#IO2 80C386EX 173#
#IO2 80C386EX 163#
#IO2 80C386EX 153#
#IO2 80C386EX 143#
#IO2 80C386EX 133#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, the Chip Select Unit, controls the pin. 
#IO3 80C386EX 153#
#IO3 80C386EX 143#
#IO3 80C386EX 133#
#IO3 80C386EX 123#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, the Interrupt Control Unit, controls the pin. 
#IO3 80C386EX 113#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, the Clock and Power Management Unit, controls the pin. 
#IO3 80C386EX 163#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, controls the pin. 
#IO3 80C386EX 173#
Determine the function of the I/O port pin. The pin can operate in either I/O mode or peripheral mode.

By selecting this option, the pin is configured to operate in peripheral mode. In this mode the peripheral function is enabled and the associated internal peripheral, controls the pin. 
#ICU 80C386EX 100#
Check this option to select level-sensitive IR input signals. Clear it to select edge-triggered IR input signals. 
#ICU 80C386EX 120#
Check this option to connect the interrupt request signal (INT0) to the package pin.  Clear it to connect the port3 pin 2 signal (P3.2) to the package pin and Vss to the master's IR1 signal. 
#ICU 80C386EX 121#
Check this option to connect the interrupt request signal (INT1) to the package pin.  Clear it to connect the port 3 pin 3 signal (P3.3) to the package pin and Vss to the master's IR5 signal. 
#ICU 80C386EX 122#
Check this option to connect the interrupt request signal (INT2) to the package pin.  Clear it to connect the port 3 pin 4 signal (P3.4) to the package pin and Vss to the master's IR6 signal. 
#ICU 80C386EX 123#
Check this option to connect the interrupt request signal (INT3) to the package pin.  Clear it to connect the port 3 pin 5 signal (P3.5) to the package pin and Vss to the master's IR7 signal. 
#ICU 80C386EX 130#
Check this option to connect the INT4 pin to the slave IR0 signal.  Clear it to connect Vss to the slave IR0 signal. 
#ICU 80C386EX 131#
Check this option to connect the INT5 pin to the slave IR1 signal.  Clear it to connect the SSIO interrupt signal (SSIOINT) to the slave IR1 signal. 
#ICU 80C386EX 132#
Check this option to connect the INT6 pin to the slave IR5 signal.  Clear it to connect Vss to the slave IR5 signal. 
#ICU 80C386EX 133#
Check this option to connect the INT7 pin to the slave IR6 signal.  Clear it to connect Vss to the slave IR6 signal. 
#ICU 80C386EX 140#
Specify which IR signals have slave 82C59As attached. 

Do NOT check this option. This bit must be cleared to guarantee device operation.  
#ICU 80C386EX 141#
Specify which IR signals have slave 82C59As attached. 

Check this option to indicate that a slave 82C59A is attached to the IR1 signal.  
#ICU 80C386EX 142#
Specify which IR signals have slave 82C59As attached. 

This option must be set (checked) because the internal slave is cascaded from the master's IR2 signal. 
#ICU 80C386EX 143#
Specify which IR signals have slave 82C59As attached. 

Do NOT check this option. This bit must be cleared to guarantee device operation. 
#ICU 80C386EX 144#
Specify which IR signals have slave 82C59As attached. 

Do NOT check this option. This bit must be cleared to guarantee device operation. 
#ICU 80C386EX 145#
Specify which IR signals have slave 82C59As attached. 

Check this option to indicate that a slave 82C59A is attached to the IR5 signal.  
#ICU 80C386EX 146#
Specify which IR signals have slave 82C59As attached. 

Check this option to indicate that a slave 82C59A is attached to the IR6 signal.  
#ICU 80C386EX 147#
Specify which IR signals have slave 82C59As attached. 

Check this option to indicate that a slave 82C59A is attached to the IR7 signal.  
#ICU 80C386EX 111#
#ICU 80C386EX 103#
Specify the interrupt base vector number. 

The base vector number corresponds to the IR0 signal's vector number and must be on an 8-byte boundary. Valid vector numbers for maskable interrupts range from 32 to 255. Since the base vector number must reside on an 8-byte boundary, the valid base vector numbers are 32 + (n x 8) where n ranges from 0 to 27. 
#ICU 80C386EX 110#
Determine which priority mode the Interrupt Control Unit will use. Check this option to enable Special-Fully Nested Mode. Clear it to enable Fully Nested Mode.

Fully Nested Mode: Allows higher level IR signals to have higher interrupt priority. Higher priority master requests suspend currently processing lower level interrupts. Higher level slave interrupt requests cannot interrupt lower level slave interrupts.

Special-Fully Nested Mode: Allows higher or equal level IR signals to have higher interrupt priority. Requests of higher or equal levels interrupt currently processing requests. Enabling this mode in the master 82C59A allows higher-level slave requests to interrupt the processing of lower-level slave interrupts.

NOTE: Another available mode is Special Mask Mode. It is not set during initialization, but can be enabled or disabled during program operation. This mode allows lower-level requests to interrupt the processing of higher-level interrupts. When enabled, only interrupts from the source currently in service are masked (disabled). 
#ICU 80C386EX 109#
Determine the method for clearing an in-service bit. Check this option to enable the Automatic End-Of-Interrupt (AEOI) Mode. Clear it to disable AEOI.

Automatic End-Of-Interrupt (AEOI)  Mode: The 82C59A clears the in-service bit at the beginning of an interrupt's processing. Therefore, interrupts of any level can interrupt the processing of other interrupts.

NOTE: There are two methods for clearing an in-service bit when AEOI is disabled, but these modes are commands issued during interrupt processing, usually at the end of an interrupt's service routine. 

Specific EOI command: Instructs the 82C59A to clear a specific IR in-service bit. 

Non-specific EOI command: Instructs the 82C59A to clear the in-service bit that corresponds to the highest level IR signal active at that time. 
#ICU 80C386EX 108#
Check this option to select level-sensitive IR input signals. Clear it to select edge-triggered IR input signals. 
#Timer0 80C386EX 100#
#Timer1 80C386EX 100#
#Timer2 80C386EX 100#
Determine the operating mode for the counter. 

Interrupt on Terminal Count Mode: Writing a count of N causes a rising edge on OUT in N+1 CLKIN pulses (provided the GATE signal remains high). The counter then waits for a new count to be written, or the counter to be reprogrammed, before resetting its OUT signal. 
#Timer0 80C386EX 101#
#Timer1 80C386EX 101#
#Timer2 80C386EX 101#
Determine the operating mode for the counter. 

Hardware Retriggerable One-Shot Mode: Writing a count of N causes a rising edge on OUT in N CLKIN pulses.  The counter waits for a gate-trigger (or reprogramming) before loading the count and resetting its OUT signal. 
#Timer0 80C386EX 102#
#Timer1 80C386EX 102#
#Timer2 80C386EX 102#
Determine the operating mode for the counter. 

Rate Generator Mode: This mode is periodic and provides a way to synchronize the counting cycle. The OUT signal remains high until the count reaches one, then goes low for one CLKIN pulse. When OUT goes high, the count is reloaded. A gate-trigger reloads the count at anytime. A high level on a counter's GATE signal enables counting; a low level disables counting. 
#Timer0 80C386EX 103#
#Timer1 80C386EX 103#
#Timer2 80C386EX 103#
Determine the operating mode for the counter. 

Square Wave Mode: This mode is periodic. A count of N results in a square wave with a period of N CLKIN pulses. A high level on a counter's GATE signal enables counting; a low level disables counting. 

NOTE: The output produced by a counter's OUT signal depends on whether a count is odd or even. 
#Timer0 80C386EX 104#
#Timer1 80C386EX 104#
#Timer2 80C386EX 104#
Determine the operating mode for the counter. 

Software-triggered Strobe Mode: Writing a count of N causes OUT to strobe low (for one CLKIN pulse) N+1 CLKIN pulses after the counter receives a gate-trigger. A high level on a counter's GATE signal enables counting; a low level disables counting. 
#Timer0 80C386EX 105#
#Timer1 80C386EX 105#
#Timer2 80C386EX 105#
Determine the operating mode for the counter. 

Hardware-triggered Strobe Mode: Writing a count of N causes OUT to strobe low (for one CLKIN pulse) N+1 CLKIN pulses after the counter receives a gate-trigger. 
#Timer0 80C386EX 140#
#Timer1 80C386EX 140#
#Timer2 80C386EX 140#
Enter the count value to be loaded into the counter. The largest possible count value is FFFFH for binary counting or 9999 for BCD counting. 
#Timer0 80C386EX 110#
#Timer1 80C386EX 110#
#Timer2 80C386EX 110#
This option selects binary counting (16 bits) as the counting format for the counter. 
#Timer0 80C386EX 111#
#Timer1 80C386EX 111#
#Timer2 80C386EX 111#
This option selects binary coded decimal counting (4 decades) as the counting format for the counter. 
#Timer0 80C386EX 120#
#Timer1 80C386EX 120#
#Timer2 80C386EX 120#
This option selects the internal prescaled clock (PSCLK) signal to be the clocking source for the timer counter. The counters can handle input frequencies up to 1/2 the processor clock, which is the maximum frequency of PSCLK (CLK2/4) . The minimum PSCLK frequency is CLK2/1026. (NOTE: The PSCLK is affected by the processor's powerdown and idle modes.)