386ex.rcd

mcs51,2051,x86系列MCU

158
REMAPCFG~ Address Configuration Register~386ex.reg~0
PORT92~ A20GATE and Fast CPU Reset~386ex.reg~1
UCSADH~ Upper Chip-select High Address~386ex.reg~153
CS0ADH~ Chip-select 0 High Address~386ex.reg~2
CS1ADH~ Chip-select 1 High Address~386ex.reg~3
CS2ADH~ Chip-select 2 High Address~386ex.reg~4
CS3ADH~ Chip-select 3 High Address~386ex.reg~5
CS4ADH~ Chip-select 4 High Address~386ex.reg~6
CS5ADH~ Chip-select 5 High Address~386ex.reg~7
CS6ADH~ Chip-select 6 High Address~386ex.reg~8
UCSADL~ Upper Chip-select Low Address~386ex.reg~154
CS0ADL~ Chip-select 0 Low Address ~386ex.reg~9
CS1ADL~ Chip-select 1 Low Address~386ex.reg~10
CS2ADL~ Chip-select 2 Low Address~386ex.reg~11
CS3ADL~ Chip-select 3 Low Address~386ex.reg~12
CS4ADL~ Chip-select 4 Low Address~386ex.reg~13
CS5ADL~ Chip-select 5 Low Address~386ex.reg~14
CS6ADL~ Chip-select 6 Low Address~386ex.reg~15
UCSMSKH~ Upper Chip-select High Mask~386ex.reg~155
CS0MSKH~ Chip-select 0 High Mask~386ex.reg~16
CS1MSKH~ Chip-select 1 High Mask~386ex.reg~17
CS2MSKH~ Chip-select 2 High Mask~386ex.reg~18
CS3MSKH~ Chip-select 3 High Mask~386ex.reg~19
CS4MSKH~ Chip-select 4 High Mask~386ex.reg~20
CS5MSKH~ Chip-select 5 High Mask~386ex.reg~21
CS6MSKH~ Chip-select 6 High Mask~386ex.reg~22
UCSMSKL~ Upper Chip-select Low Mask~386ex.reg~156
CS0MSKL~ Chip-select 0 Low Mask~386ex.reg~23
CS1MSKL~ Chip-select 1 Low Mask~386ex.reg~24
CS2MSKL~ Chip-select 2 Low Mask~386ex.reg~25
CS3MSKL~ Chip-select 3 Low Mask~386ex.reg~26
CS4MSKL~ Chip-select 4 Low Mask~386ex.reg~27
CS5MSKL~ Chip-select 5 Low Mask~386ex.reg~28
CS6MSKL~ Chip-select 6 Low Mask~386ex.reg~29
CLKPRS~ Clock Prescale Register~386ex.reg~30
DLL0~ Divisor Latch Low 0~386ex.reg~31
DLL1~ Divisor Latch Low 1~386ex.reg~32
DLH0~ Divisor Latch High 0~386ex.reg~157
DLH1~ Divisor Latch High 1~386ex.reg~158
DMABSR~ DMA Bus Size~386ex.reg~33
DMA0CHR~ DMA 0 Chaining~386ex.reg~34
DMA1CHR~ DMA 1 Chaining~386ex.reg~149
DMACMD1~ DMA Command 1~386ex.reg~35
DMACMD2~ DMA Command 2~386ex.reg~36
DMACFG~ DMA Configuration~386ex.reg~37
DMA0TAR0/1~ DMA 0 Target Address 0~386ex.reg~38
DMA0TAR2~ DMA 0 Target Address 2~386ex.reg~55
DMA0TAR3~ DMA 0 Target Address 3~386ex.reg~56
DMA1TAR0/1~ DMA 1 Target Address 0~386ex.reg~39
DMA1TAR2~ DMA 1 Target Address 2~386ex.reg~53
DMA1TAR3~ DMA 1 Target Address 3~386ex.reg~54
DMA0BYC0/1~ DMA 0 Byte Count 0~386ex.reg~40
DMA0BYC2~ DMA 0 Byte Count 2~386ex.reg~57
DMA1BYC0/1~ DMA 1 Byte Count 0~386ex.reg~41
DMA1BYC2~ DMA 1 Byte Count 2~386ex.reg~58
DMA0REQ0/1~ DMA 0 Requester Address 0~386ex.reg~42
DMA0REQ2/3~ DMA 0 Requester Address 2~386ex.reg~44
DMA1REQ0/1~ DMA 1 Requester Address 0~386ex.reg~43
DMA1REQ2/3~ DMA 1 Requester Address 2~386ex.reg~45
DMAGRPMSK~ DMA Group Channel Mask~386ex.reg~46
DMAMSK~ DMA Individual Channel Mask~386ex.reg~47
DMAIEN~ DMA Interrupt Enable~386ex.reg~48
DMAIS~ DMA Interrupt Status~386ex.reg~49
DMA0MOD1~ DMA 0 Mode 1~386ex.reg~50
DMA0MOD2~ DMA 0 Mode 2~386ex.reg~51
DMA1MOD1~ DMA 1 Mode 1~386ex.reg~152
DMA1MOD2~ DMA 1 Mode 2~386ex.reg~153
DMAOVFE~ DMA Overflow Enable~386ex.reg~52
DMASRR (read)~ DMA Software Request (Read)~386ex.reg~59
DMA0SRR (write)~ DMA 0 Software Request (Write)~386ex.reg~60
DMA1SRR (write)~ DMA 1 Software Request (Write)~386ex.reg~152
DMASTS~ DMA Status~386ex.reg~61
ICW1 (master)~ Initialization Command Word 1 (master)~386ex.reg~62
ICW1 (slave)~ Initialization Command Word 1 (slave)~386ex.reg~63
ICW2 (master)~ Initialization Command Word 2 (master)~386ex.reg~64
ICW2 (slave)~ Initialization Command Word 2 (slave)~386ex.reg~65
ICW3 (master)~ Initialization Command Word 3 (master)~386ex.reg~66
ICW3 (slave)~ Initialization Command Word 3 (slave)~386ex.reg~67
ICW4 (master)~ Initialization Command Word 4 (master)~386ex.reg~68
ICW4 (slave)~ Initialization Command Word 4 (slave)~386ex.reg~69
INTCFG~ Interrupt Configuration~386ex.reg~70
IER0~ Interrupt Enable 0~386ex.reg~71
IER1~ Interrupt Enable 1~386ex.reg~72
IIR0~ Interrupt ID 0~386ex.reg~73
IIR1~ Interrupt ID 1~386ex.reg~74
IRR (master)~ Interrupt Request (master)~386ex.reg~75
IRR (slave)~ Interrupt Request (slave)~386ex.reg~76
ISR (master)~ Interrupt In-service (master)~386ex.reg~77
ISR (slave)~ Interrupt In-service (slave)~386ex.reg~78
MCR0~ Modem Control 0~386ex.reg~79
MCR1~ Modem Control 1~386ex.reg~80
MSR0~ Modem State 0~386ex.reg~81
MSR1~ Modem State 1~386ex.reg~82
OCW1 (master)~ Operation Command Word 1 (master)~386ex.reg~83
OCW2 (master)~ Operation Command Word 2 (master)~386ex.reg~84
OCW3 (master)~ Operation Command Word 3 (master)~386ex.reg~85
OCW1 (slave)~ Operation Command Word 1 (slave)~386ex.reg~86
OCW2 (slave)~ Operation Command Word 2 (slave)~386ex.reg~87
OCW3 (slave)~ Operation Command Word 3 (slave)~386ex.reg~88
PINCFG~ Pin Configuration~386ex.reg~89
POLL (master)~ Poll Status Byte (master)~386ex.reg~90
POLL (slave)~ Poll Status Byte (slave)~386ex.reg~91
P1CFG~ Port 1 Configuration~386ex.reg~92
P2CFG~ Port 2 Configuration~386ex.reg~93
P3CFG~ Port 3 Configuration~386ex.reg~94
P1LTC~ Port 1 Data Latch~386ex.reg~95
P2LTC~ Port 2 Data Latch~386ex.reg~96
P3LTC~ Port 3 Data Latch~386ex.reg~97
P1DIR~ Port 1 Direction~386ex.reg~98
P2DIR~ Port 2 Direction~386ex.reg~99
P3DIR~ Port 3 Direction~386ex.reg~100
P1PIN~ Port 1 Pin State~386ex.reg~101
P2PIN~ Port 2 Pin State~386ex.reg~102
P3PIN~ Port 3 Pin State~386ex.reg~103
PWRCON~ Power Control Register~386ex.reg~104
RFSADD~ Refresh Address~386ex.reg~105
RFSBAD~ Refresh Base Address~386ex.reg~106
RFSCIR~ Refresh Clock Interval~386ex.reg~107
RFSCON~ Refresh Control~386ex.reg~108
LCR0~ Serial Line Control 0~386ex.reg~109
LCR1~ Serial Line Control 1~386ex.reg~110
LSR0~ Serial Line Status 0~386ex.reg~111
LSR1~ Serial Line Status 1~386ex.reg~112
SIOCFG~ SIO and SSIO Configuration~386ex.reg~113
RBR0~ SIO Receive Buffer 0~386ex.reg~114
RBR1~ SIO Receive Buffer 1~386ex.reg~115
SCR0~ SIO Scratch Pad 0~386ex.reg~116
SCR1~ SIO Scratch Pad 1~386ex.reg~117
TBR0~ SIO Transmit Buffer 0~386ex.reg~118
TBR1~ SIO Transmit Buffer 1~386ex.reg~119
SSIOBAUD~ SSIO Baud-rate Control~386ex.reg~120
SSIOCTR~ SSIO Baud-rate Count Down~386ex.reg~121
SSIOCON1~ SSIO Control 1~386ex.reg~122
SSIOCON2~ SSIO Control 2~386ex.reg~123
SSIORBUF~ SSIO Receive Holding Buffer~386ex.reg~124
SSIOTBUF~ SSIO Transmit Holding Buffer~386ex.reg~125
TMR0 (read)~ Timer 0 (Read Format)~386ex.reg~126
TMR1 (read)~ Timer 1 (Read Format)~386ex.reg~127
TMR2 (read)~ Timer 2 (Read Format)~386ex.reg~128
TMR0 (status)~ Timer 0 (Status Format)~386ex.reg~129
TMR1 (status)~ Timer 1 (Status Format)~386ex.reg~130
TMR2 (status)~ Timer 2 (Status Format)~386ex.reg~131
TMR0 (write)~ Timer 0 (Write Format)~386ex.reg~132
TMR1 (write)~ Timer 1 (Write Format)~386ex.reg~133
TMR2 (write)~ Timer 2 (Write Format)~386ex.reg~134
TMRCFG~ Timer Configuration~386ex.reg~135
TMRCON0 (ctrl word)~ Timer Control 0 (Control Word Format)~386ex.reg~136
TMRCON0 (cnt-latch)~ Timer Control 0 (Counter-latch Format)~386ex.reg~137
TMRCON1 (ctrl word)~ Timer Control 1 (Control Word Format)~386ex.reg~145
TMRCON1 (cnt-latch)~ Timer Control 1 (Counter-latch Format)~386ex.reg~146
TMRCON2 (ctrl word)~ Timer Control 2 (Control Word Format)~386ex.reg~147
TMRCON2 (cnt-latch)~ Timer Control 2 (Counter-latch Format)~386ex.reg~148
TMRCON (read-back)~ Timer Control (Read-back Format)~386ex.reg~138
WDTCNTH~ WDT Counter Value (High)~386ex.reg~139
WDTCNTL~ WDT Counter Value (Low)~386ex.reg~140
WDTRLDH~ WDT Reload Value (High)~386ex.reg~141
WDTRLDL~ WDT Reload Value (Low)~386ex.reg~142
WDTSTATUS~ WDT Status~386ex.reg~143
WDTCLR~ WDT Timer Unit~386ex.reg~144