hl386.txt

mcs51,2051,x86系列MCU

HILITES.TXT
#ICU 80C386EX#
Programmable Interrupt Control Unit\n
 - Two 8259A modules connected in master/slave configuration\n
 - Interrupt structure is compatible with PC/DOS architecture\n
 - Eight external maskable interrupt inputs\n
 - Supports up to 36 external interrupts with cascaded 82C59s\n
 - Seven internal peripheral interrupt sources\n
#BIU 80C386EX#
Bus Interface Unit\n
 - 64 Mbyte memory address range\n
 - 64 Kbyte I/O address range\n
 - 8- and 16-bit dynamic bus sizing\n
 - Separate RD# & WR# signals for glue-less SRAM & EPROM interface\n
#CSU 80C386EX#
Chip Select Unit\n
 - Eight programmable memory and peripheral chip selects\n
 - Supports SMM memory addressing\n
 - Enhances READY generation logic\n
 - Programmable wait states (0-31)\n
 - Allows overlapping of chip selects\n
 - 2 Kbyte granularity in memory address space\n
      and 2 byte granularity in I/O address space\n
 - 8-bit bus sizing logic\n
#RCU 80C386EX#
Refresh Control Unit\n
 - Provides periodic DRAM refresh cycles\n
 - Supports DRAM and PSRAM\n
 - Programmable refresh interval and address range\n
#CCB 80C386EX#
Chip Configuration Block\n
 - Pin configuration registers determine pin functions\n
 - Chip configuration registers allow versatile\n
      module inter-connection\n
 - Four processor operation modes:\n
     - DOS compatible\n
     - Non-Intrusive DOS compatible\n
     - Enhanced DOS\n
     - Non-DOS\n
#FP 80C386EX#
80C387\n
 Direct Numerics Interface to 387SX\n
#IO 80C386EX#
I/O Ports\n
 - Three flexible 8-bit I/O ports\n
      (multiplexed with other chip functions)\n
 - Individually configurable as input, output,\n
      or bidirectional open drain\n
 - CMOS level I/O\n
 - Ports 1 and 2 have 8mA drive capability\n
 - Port 3 has 16mA drive capability\n
#Serial 80C386EX#
Asynchronous Serial Ports\n
 - Two independent asynchronous serial channels (16450 compatible)\n
 - Integral programmable baud-rate generator (DC to 512Kbaud)\n
 - Modem control functions\n
 - Double-buffered transmit/receive\n
 - False start bit detection\n
 - Error detection\n
 - Fully programmable serial-interface characteristics:\n
     - 5, 6, 7, 8 bit characters\n
     - Even, odd, or no parity\n
     - Supports uLan protocol\n
     - 1, 1.5, or 2 stop bits\n
#Sync 80C386EX#
Synchronous Serial Port\n
 - Full duplex synchronous communications\n
 - Independent receiver and transmitter, capable\n
      of operating at different baud rates\n
 - Achievable transfer rates exceed 6MBaud\n
 - Integral baud rate generator\n
 - Double buffered data\n
 - Independently enabled transmit and receive functions\n
 - 16 bit serial communications\n
#WDT 80C386EX#
Watchdog Timer Unit\n
 - Allows recovery from system failures caused by runaway software\n
 - Usable as a 32-bit general-purpose timer\n
 - Bus monitor function allows recovery from "ready hang" situations\n
#Clock 80C386EX#
Clock Generating Unit\n
 - 0 to 25 MHz operation at 5 volts\n
 - 0 to 20 MHz operation at 3.3 volts\n
 - 0 to 16 MHz operation at 3.0 volts\n
 - 50% duty cycle\n
 - Static design\n
 - Programmable divider for timers and\n
      synchronous communications\n
#Timer 80C386EX#
Timer Counter Unit\n
 - 8254 compatible\n
 - Three independent 16-bit timers available\n
 - Each timer can operate in 1 of 6 modes:\n
     - Interrupt on terminal count\n
     - Hardware retriggerable one-shot\n
     - Rate generator\n
     - Square wave mode\n
     - Software triggered strobe\n
     - Hardware triggered strobe (retriggerable)\n
 - Programmable internal or external clocking source\n
#DMA 80C386EX#
Direct Memory Access Unit\n
 - Two independent DMA channels\n
 - Functional superset of the 8237A\n
 - Transfers between memory and I/O, in any combination\n
 - Transfers using 8 or 16 bit widths\n
 - Supports fly-by transfers\n
 - Internal requests (timers and SCU)\n
 - Software requests\n
 - Full 26-bit source and destination pointers\n
 - 24 bit transfer count, allowing 16Mbyte block transfers\n
#PM 80C386EX#
Power Management Unit\n
   Idle mode\n
      - Freezes CPU clock, peripherals remain active\n
      - Reduces current consumption\n
      - Exited via NMI, SMI, or unmasked interrupt\n
\n
   Powerdown mode\n
      - Freezes all internal clocks\n
      - Reduces current consumption to leakage (uA)\n
      - Exited by NMI, SMI, or unmasked external interrupt\n
#CPU 80C386EX#
CPU\n
 - Enhanced 32 bit static 386SX/SL CPU core\n
 - 132 pin JEDEC PQFP, 144 pin EIAJ TQFP packages\n
 - 26 bit address\n
 - 16 bit data\n
 - Extended temperature\n
 - System management mode (SMM) compatible with\n
      SL enhanced Intel processors\n
 - JTAG boundary scan (IEEE 1149.1 compatible) for testability\n