296saa.cod

mcs51,2051,x86系列MCU

;	**** initialize Index Registers ****
;*
;*	Index register 0 (IDX0) starts at 0$$IDX0H$$$IDX0L$h
;*	and $%TICB0.4$decrements$increments$ by $%dICB0 & 15$
;*
;*	Index register 1 (IDX1) starts at 0$$IDX1H$$$IDX1L$h
;*	and $%TICB1.4$decrements$increments$ by $%dICB1 & 15$
;*
	push	wsr
	ldb	wsr,#01Fh
	
	; initialize Index register 0
	ldb	IDX0_HI_1F,#$%AIDX0H$h
	ld	IDX0_LO_1F,#$%AIDX0L$h
	ldb	ICB0_1F,#$%AICB0$h

	; initialize Index register 1
	ldb	IDX1_HI_1F,#$%AIDX1H$h
	ld	IDX0_LO_1F,#$%AIDX1L$h
	ldb	ICB1_1F,#$%AICB1$h

	pop	wsr

$$ifp$80c296sa
cseg
$$if$ WSR.7

HOLD_CONTROL   set   080h

$$end$

$$if$ con_reg0.7
init_pwm:
  ;*   PWM is HALTED
  ;*
  SET_BIT  con_reg0,7
  ret

$$end$
$$if$ sp_con.7
init_serial:
  ;*   Baud Rate Generator is HALTED
  ;*
  SET_BIT  sp_con,7
  ret

$$end$
init_accum:
;*  initialize the accumulator options.  *
     ldb tmpreg0, #0$$ACC_STAT$h
     stb tmpreg0, ACC_STAT
     ret

$$end$
$$if$  WSR.7
init_hold_holda:
;*  init the hold, holda, and breq pins to special function  *
     ldb  wsr, #1fh
     orb  p2_reg_1F, #68h  ; Init the hold signals
     andb p2_dir_1F, #0B7h ; make hlda, breq outputs 
     orb  p2_dir_1F, #20h  ; make hold  input
     orb  p2_mode_1F, #68h ; make special function
     ldb  wsr,   #HOLD_CONTROL
     ret 

cseg at 0ff2080h
main_CPU:
     ld   sp, #STACK
$$ifp$80c296sa
     call init_accum;
  $$if$ con_reg0.7
     call init_pwm;
  $$end$
  $$if$ sp_con.7
     call init_serial;
  $$end$
$$end$
     
     ;    ****     user code    *****
     ;
     ;    To change wsr use:
     ;        ldb  wsr,   #HOLD_CONTROL + WINDOW_VALUE

     br $ 
$$end$
$$ifp$80c296sa
$$ifn$WSR.7
cseg at 0ff2080h
main_INIT:
     call init_accum;
  $$if$ con_reg0.7
     call init_pwm;
  $$end$
  $$if$ sp_con.7
     call init_serial;
  $$end$

     ;    ****     user code    *****
$$end$
$$end$
end
##80C296SA ICU#
$model(sa)
$$ifp$80c296sa
$include (80C296SA.INC)
$$end$ 

cseg
init_interrupts:
     ldb int_mask,   #$%aINT_MASK$
     ldb int_mask1,  #$%aINT_MASK1$
     ldb INT_CON0,   #$%aINT_CON0$
     ldb INT_CON1,   #$%aINT_CON1$
     ldb INT_CON2,   #$%aINT_CON2$
     ldb INT_CON3,   #$%aINT_CON3$
     ldb VECT_ADDR,  #$%aVECT_ADDR$
     ldb EXTINT_CON, #$%aEXTINT_CON$
     ret

$$if$ int_mask.0
; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2000h
timer1_ovr_vector:   dcw  lsw  timer1_ovr_isr

cseg
timer1_ovr_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.1

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2002h
timer2_ovr_vector:   dcw  lsw  timer2_ovr_isr

cseg
timer2_ovr_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.2

cseg at 0ff2004h
reserved2_vector:   dcw  lsw  reserved2_isr

cseg
reserved2_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.3

cseg at 0ff2006h
extint0_vector:   dcw  lsw  extint0_isr

cseg
extint0_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.4

cseg at 0ff2008h
extint1_vector:   dcw  lsw  extint1_isr

cseg
extint1_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.5

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Ah
TXD_vector:   dcw  lsw  TXD_isr

cseg
TXD_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK.6

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Ch
RXD_vector:   dcw  lsw  RXD_isr

cseg
RXD_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK.7

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Eh
epa0_vector:   dcw  lsw  epa0_isr

cseg
epa0_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.0

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2030h
epa1_vector:   dcw  lsw  epa1_isr

cseg
epa1_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.1

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2032h
epa2_vector:   dcw  lsw  epa2_isr

cseg
epa2_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.2

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2034h
epa3_vector:   dcw  lsw  epa3_isr

cseg
epa3_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.3

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2036h
epa0_1_ovr_vector:   dcw  lsw  epa0_1_ovr_isr

cseg
epa0_1_ovr_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.4

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2038h
epa2_3_ovr_vector:   dcw  lsw  epa2_3_ovr_isr

cseg
epa2_3_ovr_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.5

cseg at 0ff203Ah
extint2_vector:   dcw  lsw  extint2_isr

cseg
extint2_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.6

cseg at 0ff203Ch
extint3_vector:   dcw  lsw  extint3_isr

cseg
extint3_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
; The following can be used for template to handle a TRAP 
; interrupt.
;
;cseg at 0ff2010h
;dcw  LSW TRAP_isr_template
;
;cseg
;TRAP_isr_template:
;     pusha
;     
; ******** user code *******
;
;     popa
;     ret
;
; The following can be used for  template to handle a un-
; implimented opcode.
;
;cseg at 0ff2012h
;dcw   LSW UN_IMP_OPCODE_isr_template
;
;cseg
;UN_IMP_OPCODE_isr_template:
;     pusha
;
; ******** user code *******
;
;     popa
;     ret
;
; The following can be used for  template to handle a Non-
; Maskable-Interrupt.
;
;cseg at 0ff203Eh
;dcw  LSW NMI_isr_template
;
;cseg
;NMI_isr_template:
;     pusha
;
; ******** user code *******
;
;     popa
;     ret                 

cseg at 0ff2080h
main_spec_int:
     ld   sp, #STACK
     call init_interrupts
$$if$  PSW.1
     ei
$$end$     
     br   $                 ;wait for interrupts to occur
end
##80C296SA IO_P1#
$model(sa)
$$ifp$80c296sa
$include (80C296SA.INC)
$$end$

cseg
init_port1:

; p1_dir configuration:
;    $%TP1_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP1_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP1_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP1_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP1_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP1_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP1_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP1_DIR.7$IO_INPUT7$IO_OUTPUT7$;

;  p1_mode configuration:
;    $%TP1_MODE.0$IO_EPA0$LSIO_0$ + $%TP1_MODE.1$IO_EPA1$LSIO_1$ +
;    $%TP1_MODE.2$IO_EPA2$LSIO_2$ + $%TP1_MODE.3$IO_EPA3$LSIO_3$ +
;    $%TP1_MODE.4$IO_T1CLK$LSIO_4$ + $%TP1_MODE.5$T1DIR$LSIO_5$ +
;    $%TP1_MODE.6$IO_T2CLK$LSIO_6$ + $%TP1_MODE.7$IO_T2DIR$LSIO_7$;

     ldb  tmpreg0, #0$$P1_REG$h          ;initial value in p1_reg
     stb  tmpreg0, p1_reg[0]

     ldb  tmpreg0, #0$$P1_DIR$h
     stb  tmpreg0, p1_dir[0]

     ldb  tmpreg0, #0$$P1_MODE$h
     stb  tmpreg0, p1_mode[0]
     ret
end
##80C296SA IO_P2#
$model(sa)
$$ifp$80c296sa
$include (80C296SA.INC)
$$end$

cseg
init_port2:

; p2_dir configuration:
;    $%TP2_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP2_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP2_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP2_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP2_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP2_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP2_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP2_DIR.7$IO_INPUT7$IO_OUTPUT7$;

; p2_mode configuration:
;    $%TP2_MODE.0$IO_TXD$LSIO_0$ | $%TP2_MODE.1$IO_RXD$LSIO_1$ |
;    $%TP2_MODE.2$IO_EXTINT0$LSIO_2$ | $%TP2_MODE.3$IO_BREQ$LSIO_3$ |
;    $%TP2_MODE.4$IO_EXTINT1$LSIO_4$ | $%TP2_MODE.5$IO_HLD$LSIO_5$ |
;    $%TP2_MODE.6$IO_HLDA$LSIO_6$ | $%TP2_MODE.7$IO_CLKOUT$LSIO_7$;

     ldb  tmpreg0, #0$$P2_REG$h       ;initial value in p2_reg
     stb  tmpreg0, p2_reg[0]

     ldb  tmpreg0, #0$$P2_DIR$h
     stb  tmpreg0, p2_dir[0]

     ldb  tmpreg0, #0$$P2_MODE$h
     stb  tmpreg0, p2_mode[0]
     ret
end
##80C296SA IO_P3#
$model(sa)
$$ifp$80c296sa
$include (80C296SA.INC)
$$end$

cseg
init_port3:

; P3_DIR configuration:
;    $%TP3_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP3_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP3_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP3_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP3_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP3_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP3_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP3_DIR.7$IO_INPUT7$IO_OUTPUT7$;

; p3_mode configuration:
;    $%TP3_MODE.0$IO_CS0$LSIO_0$ | $%TP3_MODE.1$IO_CS1$LSIO_1$ |
;    $%TP3_MODE.2$IO_CS2$LSIO_2$ | $%TP3_MODE.3$IO_CS3$LSIO_3$ |
;    $%TP3_MODE.4$IO_CS4$LSIO_4$ | $%TP3_MODE.5$IO_CS5$LSIO_5$ |
;    $%TP3_MODE.6$IO_EXTINT2$LSIO_6$ | $%TP3_MODE.7$IO_EXTINT3$LSIO_7$;

     ldb  tmpreg0, #0$$P3_REG$h       ;initial value in p3_reg
     stb  tmpreg0, p3_reg[0]

     ldb  tmpreg0, #0$$P3_DIR$h
     stb  tmpreg0, p3_dir[0]

     ldb  tmpreg0, #0$$P3_MODE$h
     stb  tmpreg0, p3_mode[0]
     ret
end
##80C296SA IO_P4#
$model(sa)
$$ifp$80c296sa
$include (80C296SA.INC)
$$end$

cseg
init_port4:

; P4_DIR configuration:
;    $%TP4_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP4_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP4_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP4_DIR.3$IO_INPUT3$IO_OUTPUT3$  +

; p4_mode configuration:
;    $%TP4_MODE.0$IO_PWM0$LSIO_0$ | $%TP4_MODE.1$IO_PWM1$LSIO_1$ |
;    $%TP4_MODE.2$IO_PWM2$LSIO_2$;

     ldb  tmpreg0, #0$$P4_REG$h       ;initial value in p4_reg
     stb  tmpreg0, p4_reg[0]

     ldb  tmpreg0, #0$$P4_DIR$h
     stb  tmpreg0, p4_dir[0]

     ldb  tmpreg0, #0$$P4_MODE$h
     stb  tmpreg0, p4_mode[0]
     ret
end