196npa.cod

mcs51,2051,x86系列MCU

$$if$  PSW.2
     epts
$$end$
$$if$  PSW.1
     ei
$$end$
     ret

cseg at 0ff2080h
main_single_pts$%dPTS_VECTOR$:
     ld   sp, #STACK
     call Init_SingleTrans_PTS_$%dPTS_VECTOR$
     br   $

; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

; If the specific peripheral design screen is not used for the
; interrupt routine, then the following can be used for a template.
;cseg at 0ff2000h + 2 * $%dINT_VECTOR$
;dcw   lsw    End_of_PTS$%dPTS_VECTOR$
;
;cseg
;End_of_PTS$%dPTS_VECTOR$:
;     pusha
;******   User Code  ********
;     popa
;     ret
end
##80C196NP PTS_Block#
##80C196NU PTS_Block#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
PTS_BLOCK_BASE set     0380h

; This locates the PTS Block mode control block in register
; ram.  This control block may be located at any quad-word
; boundary in register space.

dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$

Block_CB_$%dPTS_VECTOR$:
Block_CB_$%dPTS_VECTOR$_ptscount:    dsb 1
Block_CB_$%dPTS_VECTOR$_ptscon:      dsb 1
Block_CB_$%dPTS_VECTOR$_ptssrc:      dsw 1
Block_CB_$%dPTS_VECTOR$_ptsdst:      dsw 1
Block_CB_$%dPTS_VECTOR$_ptsblock:    dsb 1
                                    dsb 1
; The PTS vector must contain the address of the PTS control
; block.

cseg at 0ff2040h + 2 * $%dPTS_VECTOR$
     dcw  Block_CB_$%dPTS_VECTOR$

; The following code is an example of a PTS control block
; initialization sequence.

cseg
Init_BlockTrans_PTS_$%dPTS_VECTOR$:
     ldb  tmpreg0, #0@@PTSCOUNT@h
     stb  tmpreg0, Block_CB_$%dPTS_VECTOR$_ptscount[0]
     ld   tmpreg0, #0@@PTSSRC@h
     stb  tmpreg0, Block_CB_$%dPTS_VECTOR$_ptssrc[0]
     ld   tmpreg0, #0@@PTSDST@h
     st   tmpreg0, Block_CB_$%dPTS_VECTOR$_ptsdst[0]
     ldb  tmpreg0, #0$$PTSCON$h
     stb  tmpreg0, Block_CB_$%dPTS_VECTOR$_ptscon[0]
     ldb  tmpreg0, #0@@PTSBLOCK@h
     stb  tmpreg0, Block_CB_$%dPTS_VECTOR$_ptsblock[0]
$$if$ PTSSEL_ENABLE
    SET_BIT_REGW ptssel, $%dPTS_VECTOR$
$$end$
$$if$ (PTS_VECTOR > 7)
    SET_BIT_REG int_mask1, ($%dPTS_VECTOR$-8)
$$end$
$$ifn$ (PTS_VECTOR < 8)
    SET_BIT_REG int_mask, $%dPTS_VECTOR$
$$end$
$$if$  PSW.2
     epts
$$end$
$$if$  PSW.1
     ei
$$end$
     ret

cseg at 0ff2080h
main_block_pts$%dPTS_VECTOR$:
     ld   sp, #STACK
     call Init_BlockTrans_PTS_$%dPTS_VECTOR$
     br $

; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

; If the specific peripheral design screen is not used for the
; interrupt routine, then the following can be used for a template.
;cseg at 0ff2000h + 2 * $%dINT_VECTOR$
;dcw   lsw    End_of_PTS$%dPTS_VECTOR$
;
;cseg
;End_of_PTS$%dPTS_VECTOR$:
;     pusha
;******   User Code  ********
;     popa
;     ret
end
##80C196NP PTS_PWMR#
##80C196NU PTS_PWMR#
PTS_BLOCK_BASE set     0380h
MEMORY_BLOCK_BASE  SET   0FF2000H

; This locates the PTS pwm_remap mode control block in register
; ram.  This control block may be located at any quad-word
; boundary in register space.

dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$

PWM_remap_CB_$%dPTS_VECTOR$_0:
PTS_CON   set  01H
PTS_PTR   set  02H
PTS_CONSTANT   set  04H

dsb   8        ; allocate 8 bytes

; The PTS vector must contain the address of the PTS control
; block.

cseg at MEMORY_BLOCK_BASE + 2 * $%dPTS_VECTOR$
     dcw  PWM_remap_CB_$%dPTS_VECTOR$_0

$$if$  (PTS_VECTOR > 6) && (PTS_VECTOR < 11)

; Declaration of second block of the remapped epa channel

     $$if$  (PTS_VECTOR == 7) || (PTS_VECTOR == 9)
dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$ + 8

PWM_remap_CB_$%dPTS_VECTOR$_1:
    dsb 8

cseg at MEMORY_BLOCK_BASE + 2 * $%dPTS_VECTOR$ + 2
     dcw  PWM_remap_CB_$%dPTS_VECTOR$_1

     $$end$
     $$if$  (PTS_VECTOR == 8) || (PTS_VECTOR == 10)
dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$ - 8

PWM_remap_CB_$%dPTS_VECTOR$_1:
    dsb 8

cseg at MEMORY_BLOCK_BASE + 2 * $%dPTS_VECTOR$ - 2
     dcw  PWM_remap_CB_$%dPTS_VECTOR$_1
     $$end$
$$end$

cseg
$$if$  (PTS_VECTOR < 7) || (PTS_VECTOR > 10)

; The following code is an example of a PTS control block
; initialization sequence.

Init_PWM_remap_PTS$%dPTS_VECTOR$:

     di               ;disable all Interrupts
     dpts             ;disable the PTS Interrupts

     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_CONSTANT[0]

     ld   tmpreg0, #0@@PTS_PWMR_PTR@h
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_PTR[0]

     ldb  tmpreg0, #0$$PTSCON$h
     stb  tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_CON[0]

     $$if$  (PTS_VECTOR > 7)
    SET_BIT_REG int_mask1, ($%dPTS_VECTOR$-8)
     $$end$
     $$if$  (PTS_VECTOR < 8)
    SET_BIT_REG int_mask, $%dPTS_VECTOR$
     $$end$
$$if$ PTSSEL_ENABLE
    SET_BIT ptssel, $%dPTS_VECTOR$
$$end$
     $$if$  PSW.2
     epts
     $$end$
     $$if$  PSW.1
     ei
     $$end$
     ret
$$end$
$$if$  (PTS_VECTOR > 6) && (PTS_VECTOR < 11)

; The following code is an example of a PTS control block
; initialization sequence to generate a pwm using the remap
; mode of the epa.

Init_PWM_remap_PTS$%dPTS_VECTOR$:

     di                    ;disable all Interrupts
     dpts                  ;disable the PTS Interrupts

     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_CONSTANT[0]

     ld   tmpreg0, #epa$%cPTS_VECTOR * -1 + 4$_time
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_PTR[0]

     ldb  tmpreg0, #$$PTSCON$
     stb  tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_0 + PTS_CON[0]

; Template for the second PTS channel

     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_1 + PTS_CONSTANT[0]

     $$if$  (PTS_VECTOR == 10)
     ld   tmpreg0, #epa1_time
     $$end$
     $$if$  (PTS_VECTOR == 9)
     ld   tmpreg0, #epa0_time
     $$end$
     $$if$  (PTS_VECTOR == 8)
     ld   tmpreg0, #epa3_time
     $$end$
     $$if$  (PTS_VECTOR == 7)
     ld   tmpreg0, #epa2_time
     $$end$
     st   tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_1 + PTS_PTR[0]
     ldb  tmpreg0, #0$$PTSCON$h
     stb  tmpreg0, PWM_remap_CB_$%dPTS_VECTOR$_1 + PTS_CON[0]

     $$if$ (PTS_VECTOR > 8)
    SET_BIT p1_reg,3            ;init output
    CLR_BIT p1_dir,3            ;make output
    SET_BIT p1_mode,3           ;select epa special function

    orb   int_mask1, #06         ;unmask epa2 and epa3
          $$if$  ptssel.1-2
    or    ptssel, #0600h         ;unmask pts epa2 and epa3
          $$end$
    $$end$
    $$if$ (PTS_VECTOR < 9)
    SET_BIT p1_reg,1            ;init output
    CLR_BIT p1_dir,1            ;make output
    SET_BIT p1_mode,1           ;select epa special function

    orb   int_mask, #80h        ;unmask epa0
    orb   int_mask1, #01h       ;unmask epa1
          $$if$  ptssel.7-8
    or    ptssel, #0180h         ;unmask pts epa0 and epa1
          $$end$
    $$end$
    $$if$  PSW.2
    epts
    $$end$
    $$if$  PSW.1
    ei
    $$end$
    ret

; If the epa0, epa1, or timers have not been initialized
; using a the design screens, then the following can be
; used as a template.

cseg at 0ff2080h
main_pwm_remap_pts$%dPTS_VECTOR$:
     ld   sp, #STACK
     call Init_PWM_remap_PTS$%dPTS_VECTOR$
     $$if$ (PTS_VECTOR > 8)
     ld   tmpreg0, #060h     ;timer1, compare, set output
     st   tmpreg0, epa2_con[0]
     st   zero_reg,      epa2_time[0]
     ld   tmpreg0, #0150h    ;remap, timer1, compare, clear output
     st   tmpreg0, epa3_con[0]
     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, epa3_time[0]
     $$end$
     $$if$ (PTS_VECTOR > 2)
     ld   tmpreg0, #060h     ;timer1, compare, set output
     st   tmpreg0, epa0_con[0]
     st   zero_reg,      epa0_time[0]
     ld   tmpreg0, #0150h    ;remap, timer1, compare, clear output
     st   tmpreg0, epa1_con[0]
     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, epa1_time[0]
     $$end$
     ld   tmpreg0, #0FFFFh   ;start timer at -1 to match at 0
     st   tmpreg0, timer1[0]
     ldb  tmpreg0, #0C2h     ;internal clock, 1us @16Mhz, count up
     stb  tmpreg0, t1control[0]

     br   $
     ret
$$end$
end
##80C196NP PTS_PWMT#
##80C196NU PTS_PWMT#
$model(EX)
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
PTS_BLOCK_BASE set     0380h

; This locates the PTS Block mode control block in register
; ram.  This control block may be located at any quad-word
; boundary in register space.

dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$

PWM_toggle_CB_$%dPTS_VECTOR$:
PWM_toggle_CB_$%dPTS_VECTOR$_unused:      dsb 1
PWM_toggle_CB_$%dPTS_VECTOR$_ptscon:      dsb 1
PWM_toggle_CB_$%dPTS_VECTOR$_ptsptr:      dsw 1
PWM_toggle_CB_$%dPTS_VECTOR$_ptsconst1:   dsw 1
PWM_toggle_CB_$%dPTS_VECTOR$_ptsconst2:   dsw 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 0ff2040h + 2 * $%dPTS_VECTOR$
     dcw  PWM_toggle_CB_$%dPTS_VECTOR$

cseg

; The following code is an example of a PTS control block
; initialization sequence.

Init_PWM_toggle_PTS$%dPTS_VECTOR$:
     di                 ;disable all Interrupts
     dpts               ;disable the PTS Interrupts

     ld   tmpreg0, #@@PTS_CONST1@
     st   tmpreg0, PWM_toggle_CB_$%dPTS_VECTOR$_ptsconst1[0]

     ld   tmpreg0, #@@PTS_CONST2@
     st   tmpreg0, PWM_toggle_CB_$%dPTS_VECTOR$_ptsconst2[0]

     ld   tmpreg0, #@@PTS_PWMT_PTR@
     st   tmpreg0, PWM_toggle_CB_$%dPTS_VECTOR$_ptsptr[0]

     ldb  tmpreg0, #0$$PTSCON$h
     stb  tmpreg0, PWM_toggle_CB_$%dPTS_VECTOR$_ptscon[0]

$$if$ (PTS_VECTOR > 6) && (PTS_VECTOR < 11)
; The following is example code that could be used to generate
; a PWM using an epa channel.

    SET_BIT p1_reg, 0$%XPTS_VECTOR - 7$h        ;init output
    CLR_BIT p1_dir, 0$%XPTS_VECTOR - 7$h        ;set to output
    SET_BIT p1_mode, 0$%XPTS_VECTOR - 7$h       ;set special function
$$end$
$$if$ PTSSEL_ENABLE

    SET_BIT_REGW ptssel, $%dPTS_VECTOR$
$$end$
$$if$  (PTS_VECTOR > 7)
    SET_BIT_REG int_mask1, ($%dPTS_VECTOR-8$)
$$end$
$$if$  (PTS_VECTOR < 8)
    SET_BIT_REG int_mask, $%dPTS_VECTOR$
$$end$
     ret
cseg at 0ff2080h
main_pwm_remap_pts$%dPTS_VECTOR$:
     ld   sp, #STACK
     call Init_PWM_toggle_PTS$%dPTS_VECTOR$
$$if$ (PTS_VECTOR > 6) && (PTS_VECTOR < 11)

; The following is example code that could be used to generate
; a PWM using epa$$EPA_CHANNEL$.

     ld   tmpreg0,  #070h        ;toggle, timer1, compare
     st   tmpreg0,  epa$%XPTS_VECTOR - 7$_con[0]
     ld   tmpreg0,  #@@PTS_CONST1@
     st   tmpreg0,  epa$%XPTS_VECTOR - 7$_time[0]
     ldb  tmpreg0,  #0C2h
     stb  tmpreg0,  t1control[0]
$$end$
$$if$  PSW.2
     epts
$$end$
$$if$  PSW.1
     ei
$$end$
     br   $     
end
##80C196NP IO_P1#
##80C196NU IO_P1#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg
init_port1:
     ldb  tmpreg0, #0$$P1_REG$h          ;initial value in p1_reg
     stb  tmpreg0, p1_reg[0]

; p1_dir configuration:
;    $%TP1_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP1_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP1_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP1_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP1_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP1_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP1_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP1_DIR.7$IO_INPUT7$IO_OUTPUT7$;

;  p1_mode configuration:
;    $%TP1_MODE.0$IO_EPA0$LSIO_0$ + $%TP1_MODE.1$IO_EPA1$LSIO_1$ +
;    $%TP1_MODE.2$IO_EPA2$LSIO_2$ + $%TP1_MODE.3$IO_EPA3$LSIO_3$ +
;    $%TP1_MODE.4$IO_T1CLK$LSIO_4$ + $%TP1_MODE.5$T1DIR$LSIO_5$ +
;    $%TP1_MODE.6$IO_T2CLK$LSIO_6$ + $%TP1_MODE.7$IO_T2DIR$LSIO_7$;

     ldb  tmpreg0, #0$$P1_DIR$h
     stb  tmpreg0, p1_dir[0]

     ldb  tmpreg0, #0$$P1_MODE$h
     stb  tmpreg0, p1_mode[0]
     ret
end
##80C196NP IO_P2#
##80C196NU IO_P2#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg
init_port2:
     ldb  tmpreg0, #0$$P2_REG$h       ;initial value in p2_reg
     stb  tmpreg0, p2_reg[0]

; p2_dir configuration:
;    $%TP2_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP2_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP2_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP2_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP2_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP2_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP2_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP2_DIR.7$IO_INPUT7$IO_OUTPUT7$;

; p2_mode configuration:
;    $%TP2_MODE.0$IO_TXD$LSIO_0$ | $%TP2_MODE.1$IO_RXD$LSIO_1$ |
;    $%TP2_MODE.2$IO_EXTINT0$LSIO_2$ | $%TP2_MODE.3$IO_BREQ$LSIO_3$ |
;    $%TP2_MODE.4$IO_EXTINT1$LSIO_4$ | $%TP2_MODE.5$IO_HLD$LSIO_5$ |
;    $%TP2_MODE.6$IO_HLDA$LSIO_6$ | $%TP2_MODE.7$IO_CLKOUT$LSIO_7$;

     ldb  tmpreg0, #0$$P2_DIR$h
     stb  tmpreg0, p2_dir[0]

     ldb  tmpreg0, #0$$P2_MODE$h
     stb  tmpreg0, p2_mode[0]
     ret
end
##80C196NP IO_P3#
##80C196NU IO_P3#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg
init_port3:
     ldb  tmpreg0, #0$$P3_REG$h       ;initial value in p3_reg
     stb  tmpreg0, p3_reg[0]

; P3_DIR configuration:
;    $%TP3_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP3_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP3_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP3_DIR.3$IO_INPUT3$IO_OUTPUT3$  +
;    $%TP3_DIR.4$IO_INPUT4$IO_OUTPUT4$ + $%TP3_DIR.5$IO_INPUT5$IO_OUTPUT5$  +
;    $%TP3_DIR.6$IO_INPUT6$IO_OUTPUT6$ + $%TP3_DIR.7$IO_INPUT7$IO_OUTPUT7$;

; p3_mode configuration:
;    $%TP3_MODE.0$IO_CS0$LSIO_0$ | $%TP3_MODE.1$IO_CS1$LSIO_1$ |
;    $%TP3_MODE.2$IO_CS2$LSIO_2$ | $%TP3_MODE.3$IO_CS3$LSIO_3$ |
;    $%TP3_MODE.4$IO_CS4$LSIO_4$ | $%TP3_MODE.5$IO_CS5$LSIO_5$ |
;    $%TP3_MODE.6$IO_EXTINT2$LSIO_6$ | $%TP3_MODE.7$IO_EXTINT3$LSIO_7$;

     ldb  tmpreg0, #0$$P3_DIR$h
     stb  tmpreg0, p3_dir[0]

     ldb  tmpreg0, #0$$P3_MODE$h
     stb  tmpreg0, p3_mode[0]
     ret
end
##80C196NP IO_P4#
##80C196NU IO_P4#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg
init_port4:
     ldb  tmpreg0, #0$$P4_REG$h       ;initial value in p4_reg
     stb  tmpreg0, p4_reg[0]

; P4_DIR configuration:
;    $%TP4_DIR.0$IO_INPUT0$IO_OUTPUT0$ + $%TP4_DIR.1$IO_INPUT1$IO_OUTPUT1$  +
;    $%TP4_DIR.2$IO_INPUT2$IO_OUTPUT2$ + $%TP4_DIR.3$IO_INPUT3$IO_OUTPUT3$  +

; p4_mode configuration:
;    $%TP4_MODE.0$IO_PWM0$LSIO_0$ | $%TP4_MODE.1$IO_PWM1$LSIO_1$ |
;    $%TP4_MODE.2$IO_PWM2$LSIO_2$;

     ldb  tmpreg0, #0$$P4_DIR$h
     stb  tmpreg0, p4_dir[0]

     ldb  tmpreg0, #0$$P3_MODE$h
     stb  tmpreg0, p3_mode[0]
     ret
end