196npa.cod

mcs51,2051,x86系列MCU

     $$if$ P2_MODE.0 &! P2_MODE.1
     push #041h                     ;pass the 'A' character
     call putchar                   ;transmitt a character
     add  sp, #2
     br   $
     $$end$
     $$ifn$ P2_MODE.0 && P2_MODE.1
do_while_not_Q
     call getchar
     cmpb tmpreg0, #051h           ;check for letter 'Q'
     bne  do_while_not_Q
     br   $
     $$end$
$$end$
end
##80C196NP PM#
##80C196NP BIU#
##80C196NP CPU#
##80C196NP CODE#
##80C196NU PM#
##80C196NU BIU#
##80C196NU CPU#
##80C196NU CODE#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg at 0ff2018h
;     ****  chip configuration: ****
;*
;* Number of wait states = $%4CCR0.4-5$Zero$One$Two$Three$ wait states
;* Powerdown Mode = $%ECCR0.0$
;* Bus Mode = $%TCCR0.3$Demultiplexed$Multiplexed$
;* Write control mode = $%TCCR0.2$Standard BHE mode$Write strobe WRH$
;* Bus width = $%TCCR0.1$Sixteen$Eight$ bit bus
;* Addressing mode = $%TCCR1.1$64 Kbyte$1 Mbyte$
$$ifp$80c196np
;* ROM remapping = $%TCCR1.2$ROM mapped to 0 and 0FFh$ROM mapped to 0FFh$
$$end$
$$ifp$80c196nu
;* Deferred Mode = $%ECCR1.5$
;
;     ****  Accumulator Options: ****
;*
;* Saturation Mode = $%EACC_STAT.6$
;* Fractional Mode = $%EACC_STAT.7$
$$end$

ccr0:     dcw  0$$CCR0$h
ccr1:     dcw  0$$CCR1$h

$$ifp$80c196nu
cseg
$$if$ WSR.7

HOLD_CONTROL   set   080h

$$end$
init_accum:
;*  initialize the accumulator options.  *
     ldb ACC_STAT, #0$$ACC_STAT$h
     ret

$$end$
$$if$  WSR.7
$$ifp$80c196np
cseg

HOLD_CONTROL   set   080h

$$end$
init_hold_holda:
;*  init the hold, holda, and breq pins to special function  *
     ldb  wsr, #1fh
     orb  p2_reg_1F, #68h  ; Init the hold signals
     andb p2_dir_1F, #0B7h ; make hlda, breq outputs 
     orb  p2_dir_1F, #20h  ; make hold  input
     orb  p2_mode_1F, #68h ; make special function
     ldb  wsr,   #HOLD_CONTROL
     ret 

cseg at 0ff2080h
main_CPU:
     ld   sp, #STACK
$$ifp$80c196nu
     call init_accum;
$$end$
     
     ;    ****     user code    *****
     ;
     ;    To change wsr use:
     ;        ldb  wsr,   #HOLD_CONTROL + WINDOW_VALUE

     br $ 
$$end$
$$ifp$80c196nu
$$ifn$WSR.7
cseg at 0ff2080h
main_INIT:
     call init_accum;

     ;    ****     user code    *****
$$end$
$$end$
end
##80C196NP ICU#
##80C196NU ICU#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$ 

cseg
init_interrupts:
     ldb int_mask, #$%aINT_MASK$
     ldb int_mask1, #$%aINT_MASK1$
     ret

$$if$ int_mask.0
; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2000h
timer1_ovr_vector:   dcw  lsw  timer1_ovr_isr

cseg
timer1_ovr_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.1

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2002h
timer2_ovr_vector:   dcw  lsw  timer2_ovr_isr

cseg
timer2_ovr_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.2

cseg at 0ff2004h
reserved2_vector:   dcw  lsw  reserved2_isr

cseg
reserved2_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.3

cseg at 0ff2006h
extint0_vector:   dcw  lsw  extint0_isr

cseg
extint0_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.4

cseg at 0ff2008h
extint1_vector:   dcw  lsw  extint1_isr

cseg
extint1_isr:
     pusha
     ;  User Code
     popa
     ret
$$end$
$$if$ INT_MASK.5

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Ah
TXD_vector:   dcw  lsw  TXD_isr

cseg
TXD_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK.6

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Ch
RXD_vector:   dcw  lsw  RXD_isr

cseg
RXD_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK.7

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff200Eh
epa0_vector:   dcw  lsw  epa0_isr

cseg
epa0_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.0

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2030h
epa1_vector:   dcw  lsw  epa1_isr

cseg
epa1_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.1

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2032h
epa2_vector:   dcw  lsw  epa2_isr

cseg
epa2_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.2

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2034h
epa3_vector:   dcw  lsw  epa3_isr

cseg
epa3_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.3

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2036h
epa0_1_ovr_vector:   dcw  lsw  epa0_1_ovr_isr

cseg
epa0_1_ovr_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.4

; Enabling of the this direct Interrupt should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      

cseg at 0ff2038h
epa2_3_ovr_vector:   dcw  lsw  epa2_3_ovr_isr

cseg
epa2_3_ovr_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.5

cseg at 0ff203Ah
extint2_vector:   dcw  lsw  extint2_isr

cseg
extint2_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
$$if$ INT_MASK1.6

cseg at 0ff203Ch
extint3_vector:   dcw  lsw  extint3_isr

cseg
extint3_isr:
     pusha
     ;  User Code
     popa
     ret

$$end$
; The following can be used for template to handle a TRAP 
; interrupt.
;
;cseg at 0ff2010h
;dcw  LSW TRAP_isr_template
;
;cseg
;TRAP_isr_template:
;     pusha
;     
; ******** user code *******
;
;     popa
;     ret
;
; The following can be used for  template to handle a un-
; implimented opcode.
;
;cseg at 0ff2012h
;dcw   LSW UN_IMP_OPCODE_isr_template
;
;cseg
;UN_IMP_OPCODE_isr_template:
;     pusha
;
; ******** user code *******
;
;     popa
;     ret
;
; The following can be used for  template to handle a Non-
; Maskable-Interrupt.
;
;cseg at 0ff203Eh
;dcw  LSW NMI_isr_template
;
;cseg
;NMI_isr_template:
;     pusha
;
; ******** user code *******
;
;     popa
;     ret                 

cseg at 0ff2080h
main_spec_int:
     ld   sp, #STACK
     call init_interrupts
$$if$  PSW.1
     ei
$$end$     
     br   $                 ;wait for interrupts to occur
end
##80C196NP PTS#
##80C196NU PTS#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$

cseg
init_global_pts:

; ***  enabled pts events: ****
$$if$ PTSSEL.0
;              PTS TIMER1 OVR
$$end$
$$if$ PTSSEL.1
;              PTS TIMER2 OVR
$$end$
$$if$ PTSSEL.3
;              PTS EXTINT0
$$end$
$$if$ PTSSEL.4
;              PTS EXTINT1
$$end$
$$if$ PTSSEL.5
;              PTS TXD
$$end$
$$if$ PTSSEL.6
;              PTS RXD
$$end$
$$if$ PTSSEL.7
;              PTS EPA0
$$end$
$$if$ PTSSEL.8
;              PTS EPA1
$$end$
$$if$ PTSSEL.9
;              PTS EPA2 
$$end$
$$if$ PTSSEL.10
;              PTS EPA3
$$end$
$$if$ PTSSEL.11
;              PTS EPA0_1 OVR
$$end$
$$if$ PTSSEL.12
;              PTS EPA2_3 OVR
$$end$
$$if$ PTSSEL.13
;              PTS EXTINT2
$$end$
$$if$ PTSSEL.14
;              PTS EXTINT3
$$end$

     ld  ptssel, #0$$PTSSEL$h
$$if$ PSW.2
     epts
$$end$
     ret
end
##80C196NP PTS_Single#
##80C196NU PTS_Single#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
PTS_BLOCK_BASE set     0380h
; PTS vector $%dPTS_VECTOR$
;
; This locates the PTS Single mode control block in register
; ram.  This control block may be located at any quad-word
; boundary in register space.

dseg  at  PTS_BLOCK_BASE + 8 * $%dPTS_VECTOR$

Single_CB_$%dPTS_VECTOR$:
Single_CB_$%dPTS_VECTOR$_ptscount:    dsb 1
Single_CB_$%dPTS_VECTOR$_ptscon:      dsb 1
Single_CB_$%dPTS_VECTOR$_ptssrc:      dsw 1
Single_CB_$%dPTS_VECTOR$_ptsdst:      dsw 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 0ff2040h + 2 * $%dPTS_VECTOR$
     dcw  Single_CB_$%dPTS_VECTOR$
     
; The following code is an example of a PTS control block
; initialization sequence.

cseg
Init_SingleTrans_PTS_$%dPTS_VECTOR$:
     ldb  tmpreg0, #0@@PTSCOUNT@h
     stb  tmpreg0, Single_CB_$%dPTS_VECTOR$_ptscount[0]
     ld   tmpreg0, #0@@PTSSRC@h
     stb  tmpreg0, Single_CB_$%dPTS_VECTOR$_ptssrc[0]
     ld   tmpreg0, #0@@PTSDST@h
     st   tmpreg0, Single_CB_$%dPTS_VECTOR$_ptsdst[0]
     ldb  tmpreg0, #0$$PTSCON$h
     stb  tmpreg0, Single_CB_$%dPTS_VECTOR$_ptscon[0]
$$if$ PTSSEL_ENABLE
    SET_BIT_REGW ptssel, $%dPTS_VECTOR$
$$end$
$$if$ (PTS_VECTOR > 7)
    SET_BIT_REG int_mask1, ($%dPTS_VECTOR$-8)
$$end$
$$if$ (PTS_VECTOR < 8)
    SET_BIT_REG int_mask, $%dPTS_VECTOR$
$$end$