📄 196npa.cod
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/*
* Copyright (c) 1995, Intel Corporation
*
* $Workfile: 196npa.cod $
* $Revision: 1.3 $
* $Modtime: Apr 13 1995 08:20:22 $
*
* Purpose:
*
*
*
*
*
* Compiler:
*
* Ext Packages:
*
*
*
*/
##80C196?? WRITE#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
$$IFSTR$ REG_MNEM "CCR0"
cseg at 0ff2018h
ccr0: dcw 0$%XREG_VALUE & 0xFF$h
$$END$
$$IFSTR$ REG_MNEM "CCR1"
cseg at 0ff2018h
ccr0: dcw 0$%XCCR0 & 0xFF$h
ccr1: dcw 0$%XREG_VALUE & 0xFF$h
$$END$
$$IFSTR$ REG_MNEM "CCR2"
cseg at 0ff2018h
ccr0: dcw 0$%XCCR0 & 0xFF$h
ccr1: dcw 0$%XCCR1 & 0xFF$h
ccr2: dcw 0$%XREG_VALUE & 0xFF$h
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
LD@@REG_SIZE@ @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, #$%aREG_VALUE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
##80C196?? READ#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
LD@@REG_SIZE@ UserVar, @@REG_MNEM@_$$REG_WSR$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
##80C196?? OR#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
OR@@REG_SIZE@ @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
OR@@REG_SIZE@ UserVar, #$%aREG_VALUE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
##80C196?? AND#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
AND@@REG_SIZE@ @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
AND@@REG_SIZE@ UserVar, #$%aREG_VALUE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
##80C196?? XOR#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
XOR@@REG_SIZE@ @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
XOR@@REG_SIZE@ UserVar, #$%aREG_VALUE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
##80C196?? TESTZ#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
AND@@REG_SIZE@ zero_reg, @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
AND@@REG_SIZE@ zero_reg, UserVar, #00H
$$END$
JE <Dest. Label>
$$END$
##80C196?? TESTNZ#
$$IFSTR$ REG_MNEM "CCR0" |STR "CCR1" |STR "CCR2"
The Chip Configuration Byte is a ROM location.
Select WRITE to configure CCB's
$$END$
$$ELSE$
$$IF$ REG_USEWSR
LDB wsr, #$%aREG_WSR$
AND@@REG_SIZE@ zero_reg, @@REG_MNEM@_$$REG_WSR$, #$%aREG_VALUE$
$$END$
$$IFN$ REG_USEWSR
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
AND@@REG_SIZE@ zero_reg, UserVar, #00H
$$END$
JNE <Dest. Label>
$$END$
##80C196NP PWM0#
##80C196NP PWM1#
##80C196NP PWM2#
##80C196NU PWM0#
##80C196NU PWM1#
##80C196NU PWM2#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
PWM_PRESCALE0 set 0
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
PWM_PRESCALE0 set 0
PWM_PRESCALE1 set 1
$$end$
cseg
init_pwm$$PWM_NUMBER$:
;* PWM$$PWM_NUMBER$ configuration:
;* prescaler mode = divide by $%4con_reg0.0-1$1$2$2$4$
$$if$ (PWM_NUMBER == 0)
;* PWM output = $%tp4_mode.0$enabled$disabled$
$$end$
$$if$ (PWM_NUMBER == 1)
;* PWM output = $%tp4_mode.1$enabled$disabled$
$$end$
$$if$ (PWM_NUMBER == 2)
;* PWM output = $%tp4_mode.2$enabled$disabled$
$$end$
;* PWM duty cycle = @@PWM_DUTY_CYCLE@ %
;*
;* pwm$$PWM_NUMBER$_control = 256 * (Duty Cycle) / 100
ldb wsr, #1Fh ; 128 byte window @ 1f80h
$%tcon_reg0.0$SET$CLR$_BIT con_reg0_1F, PWM_PRESCALE0
$$ifp$80c196nu
$%tcon_reg0.1$SET$CLR$_BIT con_reg0_1F, PWM_PRESCALE1
$$end$
$$if$ (PWM_NUMBER == 0)
ldb pwm$$PWM_NUMBER$_control_1F, # 0$$PWM0_CONTROL$h
$$if$ P4_MODE.0
andb p4_dir_1F, #$%3PWM_NUMBER$0FE$0FD$0FB$h
orb p4_mode_1F, #$%3PWM_NUMBER$1$2$4$
$$end$
$$end$
$$if$ (PWM_NUMBER == 1)
ldb pwm$$PWM_NUMBER$_control_1F, # 0$$PWM1_CONTROL$h
$$if$ P4_MODE.1
andb p4_dir_1F, #$%3PWM_NUMBER$0FE$0FD$0FB$h
orb p4_mode_1F, #$%3PWM_NUMBER$1$2$4$
$$end$
$$end$
$$if$ (PWM_NUMBER == 2)
ldb pwm$$PWM_NUMBER$_control_1F, # 0$$PWM2_CONTROL$h
$$if$ P4_MODE.2
andb p4_dir_1F, #$%3PWM_NUMBER$0FE$0FD$0FB$h
orb p4_mode_1F, #$%3PWM_NUMBER$1$2$4$
$$end$
$$end$
ret
cseg at 0ff2080h
pwm$$PWM_NUMBER$_main:
ld sp, #STACK
call init_pwm$$PWM_NUMBER$
br $
end
##80C196NP CSU#
##80C196NU CSU#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
MUXED_BUS set 0
DEMUXED_BUS set 80h
BW_8 set 0
BW_16 set 40h
WS_0 set 0
WS_1 set 1
WS_2 set 2
WS_3 set 3
cseg at 0FF2080h
Init_ChipSelects:
ldb wsr, #3Dh ; 64-byte window @ 1f40h
ld addrmsk0_3D, zero_reg ; Init to large range
; start address end address
ld addrcom0_3D, #$%Aaddrcom0$ ; @@startaddr0@ @@endaddr0@
ld addrmsk0_3D, #$%Aaddrmsk0$
ld addrcom1_3D, #$%Aaddrcom1$ ; @@startaddr1@ @@endaddr1@
ld addrmsk1_3D, #$%Aaddrmsk1$
ld addrcom2_3D, #$%Aaddrcom2$ ; @@startaddr2@ @@endaddr2@
ld addrmsk2_3D, #$%Aaddrmsk2$
ld addrcom3_3D, #$%Aaddrcom3$ ; @@startaddr3@ @@endaddr3@
ld addrmsk3_3D, #$%Aaddrmsk3$
ld addrcom4_3D, #$%Aaddrcom4$ ; @@startaddr4@ @@endaddr4@
ld addrmsk4_3D, #$%Aaddrmsk4$
ld addrcom5_3D, #$%Aaddrcom5$ ; @@startaddr4@ @@endaddr5@
ld addrmsk5_3D, #$%Aaddrmsk5$
ldb buscon0_3D, #$%Tbuscon0.7$DE$$MUXED_BUS + BW_$%Tbuscon0.6$16$8$ + WS_$%Xbuscon0 & 3$
ldb buscon1_3D, #$%Tbuscon1.7$DE$$MUXED_BUS + BW_$%Tbuscon1.6$16$8$ + WS_$%Xbuscon1 & 3$
ldb buscon2_3D, #$%Tbuscon2.7$DE$$MUXED_BUS + BW_$%Tbuscon2.6$16$8$ + WS_$%Xbuscon2 & 3$
ldb buscon3_3D, #$%Tbuscon3.7$DE$$MUXED_BUS + BW_$%Tbuscon3.6$16$8$ + WS_$%Xbuscon3 & 3$
ldb buscon4_3D, #$%Tbuscon4.7$DE$$MUXED_BUS + BW_$%Tbuscon4.6$16$8$ + WS_$%Xbuscon4 & 3$
ldb buscon5_3D, #$%Tbuscon5.7$DE$$MUXED_BUS + BW_$%Tbuscon5.6$16$8$ + WS_$%Xbuscon5 & 3$
ldb wsr, #3Fh ; 64 byte window @ 1FC0h
orb p3_reg_3F, #$%Ap3_mode$ ; initialize the reg register
andb p3_dir_3F, #$%Ap3_mode ^ 0xFF$ ; configure I/O
orb p3_mode_3F, #$%Ap3_mode$ ; enable the chip selects
br $ ; Should jump to user code
end
##80C196NP IO_EP#
##80C196NQ IO_EP#
##80C196NU IO_EP#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
cseg
init_eport:
ldb tmpreg0, #$%aEP_REG$ ; initial value in ep_reg
stb tmpreg0, ep_reg[0]
; ep_dir configuration:
; $%TEP_DIR.0$IO_INPUT0$IO_OUTPUT0$ | $%TEP_DIR.1$IO_INPUT1$IO_OUTPUT1$ |
; $%TEP_DIR.2$IO_INPUT2$IO_OUTPUT2$ | $%TEP_DIR.3$IO_INPUT3$IO_OUTPUT3$ |
;
; ep_mode configuration:
; $%TEP_MODE.0$EXT_BUS_A16$LSIO_0$ | $%TEP_MODE.1$EXT_BUS_A17$LSIO_1$ |
; $%TEP_MODE.2$EXT_BUS_A18$LSIO_2$ | $%TEP_MODE.3$EXT_BUS_A19$LSIO_3$ |
ldb tmpreg0, #0$$EP_DIR$h
stb tmpreg0, ep_dir[0]
ldb tmpreg0, #0$$EP_MODE$h
stb tmpreg0, ep_mode[0]
ret
end
##80C196NP EPA#
##80C196NU EPA#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
CAPTURE set 000h
COMPARE set 040h
EPA_ATOD set 004h
RE_ENABLE set 008h
POS_EDGE set 020h
SET_PIN set 020h
NEG_EDGE set 010h
CLR_PIN set 010h
BOTH_EDGE set 030h
TOGGLE_PIN set 030h
NOTHING set 000h
RESET_OPP_TIMER set 002h
RESET_TIMER set 001h
OVERWRITE_NEW_DATA set 001h
IGNORE_NEW_DATA set 000h
USE_TIMER1 set 000h
USE_TIMER2 set 080h
RE_MAP set 00100h
EPA0_INT_BIT set 7
EPA1_INT_BIT set 0
EPA2_INT_BIT set 1
EPA3_INT_BIT set 2
EPA0_1_OVR_INT_BIT set 3
EPA2_3_OVR_INT_BIT set 4
cseg
init_epa$$EPA_CHANNEL$:
; init_epa$$EPA_CHANNEL$:
; Program the EPA module $$EPA_CHANNEL$ to operate in $%tEPA_CON.6$compare$capture$ mode
; using $%tEPA_CON.7$timer 2$timer 1$ as the reference timer.
$$ifn$ EPA_CON.6 && EPA_CON.1 || EPA_CON.0 || EPA_CON.5 || EPA_CON.4 || EPA_CON.2
;
; Select the following actions as $%tEPA_CON.6$compare$capture$ event(s):
$$if$ EPA_CON.6
$$if$ EPA_CON.4 || EPA_CON.5
; - $%4EPA_CON.4-5$$clear$set$toggle$ the EPA output pin
$$end$
$$end$
$$else$
$$if$ EPA_CON.4 || EPA_CON.5
; - $%4EPA_CON.4-5$$falling$rising$either$ edge on the EPA input pin
$$end$
$$end$
$$if$ EPA_CON.2
; - start an A/D conversion
$$end$
$$if$ EPA_CON.0 && EPA_CON.6
$$if$ EPA_CON.1
; - reset $%tEPA_CON.7$timer 1$timer 2$
$$end$
$$ifn$ EPA_CON.1
; - reset $%tEPA_CON.7$timer 2$timer 1$
$$end$
$$end$
$$if$ EPA_CON.1 &! EPA_CON.6
; - reset $%tEPA_CON.7$timer 1$timer 2$
$$end$
$$end$
$$ifn$ EPA_CON.6
;
; Configure the module to $%tEPA_CON.0$overwrite old data in the buffer$ignore new data$ when an
; overrun error is generated.
$$end$
$$if$ EPA_CON.3 && EPA_CON.6
;
; Set the reenable bit so that the compare function is always enabled.
$$end$
ld tmpreg0, #0$$EPA_CON$h
st tmpreg0, epa$$EPA_CHANNEL$_con[0]
$$if$ EPA_CON.6
$$if$ RELATIVE
; Load the EPA$$EPA_CHANNEL$_TIME register with the $%TEPA_CON.7$timer 2$timer 1$ value
; plus an offset of $$TIMER_OFFSET$h.
ld tmpreg0, $%TEPA_CON.7$timer2$timer1$[0]
add tmpreg0, #0$$TIMER_OFFSET$h
st tmpreg0, epa$$EPA_CHANNEL$_time[0]
$$end$
$$ifn$ RELATIVE
; Load the EPA$$EPA_CHANNEL$_TIME register with the $$TIMER_OFFSET$h.
ld tmpreg0, #0$$TIMER_OFFSET$h
st tmpreg0, epa$$EPA_CHANNEL$_time[0]
$$end$
$$end$
$$if$ EPA_CON.4-5
; Configure the port pin as an EPA event pin.
SET_BIT p1_reg, $$EPA_CHANNEL$ ;init reg
$$if$ EPA_CON.6
CLR_BIT p1_dir, $$EPA_CHANNEL$ ;make output pin
$$end$
$$else$
SET_BIT p1_dir, $$EPA_CHANNEL$ ;make input pin
$$end$
SET_BIT p1_mode, $$EPA_CHANNEL$ ;select EPA mode
$$end$ end of port setup
$$if$ EPA_INTERRUPT
SET_BIT_REG $%TEPA_CHANNEL$int_mask1$int_mask$, EPA$$EPA_CHANNEL$_INT_BIT ;unmask epa interrupts
$$end$
$$if$ EPA_OVERFLOW
SET_BIT_REG int_mask1, EPA$%TEPA_CHANNEL.1$2_3$0_1$_OVR_INT_BIT ;unmask epax interrupts
$$end$
ret
$$ifn$ EPA_OVERFLOW &! EPA_INTERRUPT
poll_epa$$EPA_CHANNEL$:
$$if$ (EPA_CHANNEL == 0)
jbc int_pend, EPA$$EPA_CHANNEL$_INT_BIT, no_epa$$EPA_CHANNEL$_interrupts
$$end$
$$else$
jbc int_pend1, EPA$$EPA_CHANNEL$_INT_BIT, no_epa$$EPA_CHANNEL$_interrupts
$$end$
; User code for event channel $$EPA_CHANNEL$ would go here
$$ifn$ EPA_CON.6
ld tmpreg0, epa$$EPA_CHANNEL$_time[0] ;time needs to be read to
;avoid overrun
$$end$
$$if$ EPA_CON.6 &! EPA_CON.3
; Since this event was not re-enabled, no more events will occur.
$$end$
$$if$ RELATIVE && EPA_CON.6 && EPA_CON.3
ld tmpreg0, epa$$EPA_CHANNEL$_time[0]
add tmpreg0, #0$$TIMER_OFFSET$h
st tmpreg0, epa$$EPA_CHANNEL$_time[0]
$$end$
$$ifn$ RELATIVE && EPA_CON.6 && EPA_CON.3
; Since this event is absolute and re-enabled,
; no polling is necessary.
$$end$
$$if$ (EPA_CHANNEL == 0)
CLR_BIT int_pend, EPA$$EPA_CHANNEL$_INT_BIT
$$end$
$$else$
CLR_BIT int_pend1, EPA$$EPA_CHANNEL$_INT_BIT
$$end$
no_epa$$EPA_CHANNEL$_interrupts:
ret
$$end$
cseg at 0ff2080h
main_epa$$EPA_CHANNEL$:
ld sp, #STACK
; Should init the timers before using the epa
call init_epa$$EPA_CHANNEL$
$$if$ EPA_INTERRUPT || EPA_OVERFLOW
ei ;globally enable interrupts
br $ ;wait for interrupts to occur
$$end$
$$else$
; EPA events can be serviced by polling int_pend or epa_pend.
loop_forever$$EPA_CHANNEL$:
call poll_epa$$EPA_CHANNEL$
br loop_forever$$EPA_CHANNEL$
$$end$
$$if$ EPA_INTERRUPT
cseg at 0ff20$%4EPA_CHANNEL$0e$30$32$34$h
epa$$EPA_CHANNEL$_vector: dcw LSW epa$$EPA_CHANNEL$_interrupt
cseg
epa$$EPA_CHANNEL$_interrupt:
pusha
push tmpreg0
$$ifn$ EPA_CON.6
ld tmpreg0, epa$$EPA_CHANNEL$_time[0] ;time needs to be read to
;avoid overrun
$$end$
$$if$ EPA_CON.6 && RELATIVE && EPA_CON.3
ld tmpreg0, epa$$EPA_CHANNEL$_time[0]
add tmpreg0, #0$$TIMER_OFFSET$h
st tmpreg0, epa$$EPA_CHANNEL$_time[0]
$$end$
$$if$ EPA_CON.6 &! EPA_CON.3
; Since not re-enabled, no more events will occur unless
; epa_control and epa_time are re-written.
$$end$
$$ifn$ RELATIVE && EPA_CON.6 && EPA_CON.3
; Since this event is absolute and re-enabled,
; user code does not need to re-enable.
$$end$
pop tmpreg0
popa
ret
$$end$
$$if$ EPA_OVERFLOW
cseg at 0ff20$%TEPA_CHANNEL.1$38$36$h
epa$%TEPA_CHANNEL.1$2_3$0_1$_OVR_vector: dcw LSW epa$%TEPA_CHANNEL.1$2_3$0_1$_OVR_interrupt
cseg
epa$%TEPA_CHANNEL.1$2_3$0_1$_OVR_interrupt:
pusha
push tmpreg0
ld tmpreg0, epa$$EPA_CHANNEL$_time[0] ;time needs to be read to
;to clear overrun
; User's code to handle overrun.
pop tmpreg0
popa
ret
$$end$
end
##80C196NP TIMER#
##80C196NU TIMER#
$$ifp$80c196np
$model(NP)
$include (80C196NP.INC)
$$end$
$$ifp$80c196nu
$model(NU)
$include (80C196NU.INC)
$$end$
COUNT_ENABLE set 080h
COUNT_DISABLE set 000h
COUNT_UP set 040h
COUNT_DOWN set 000h
CLOCK_INTERNAL set 000h
CLOCK_EXTERNAL set 008h
DIRECTION_TXDIR set 010h
CLOCK_T1_OVFL set 020h
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