196kxa.cod

mcs51,2051,x86系列MCU

no_ov$$SSIO_CHANNEL$_error_rec:
           $$ifn$ SSIO_CON.2

; ****  re enable a transfer   ****

     ldb   tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
     orb   tmpreg0, #SSIO_TRANSFER_ENABLE
     stb   tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
           $$end$

;****   return the received byte   ******

     ldb   tmpreg0, ssio$$SSIO_CHANNEL$_buf[0]
     ret
     $$end$
$$end$

$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2080h
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02080h
$$end$
main_ssio$$SSIO_CHANNEL$:
     ld    sp, #STACK
     call  init_ssio$$SSIO_CHANNEL$
$$if$ SSIO_INTERRUPT
     ei                         ;global enable interrupts
     $$if$  SSIO_CON.6
           $$ifn$ SSIO_CON.4
     ldb   tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
     orb   tmpreg0, #SSIO_TRANSFER_ENABLE
     stb   tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
           $$end$
     stb   zero_reg, ssio$$SSIO_CHANNEL$_buf[0]   ;start the transmissions 
     $$end$
     br $                       ;wait around for interrupt
$$end$
$$ifn$ SSIO_INTERRUPT
     stb   zero_reg, ssio$$SSIO_CHANNEL$_buf[0]  ;Used to start transmitter
do_forever_ssio$$SSIO_CHANNEL$:
     $$if$  SSIO_CON.6
     push  #041h               ;transmit a 'A'
     call  ssio$$SSIO_CHANNEL$_putchar
     add   sp, #2               ;clean parameter off stack
     $$end$
     $$ifn$  SSIO_CON.6
     call  ssio$$SSIO_CHANNEL$_getchar
     ; stb  tmpreg0, somewhere[0]   ;store some place
     $$end$
     br    do_forever_ssio$$SSIO_CHANNEL$
$$end$
end
##80C196NT SlvPrt#
##80C196NQ SlvPrt#
##80C196KT SlvPrt#
##80C196KQ SlvPrt#
##80C196KR SlvPrt#
##80C196JR SlvPrt#
##80C196JT SlvPrt#
##80C196JQ SlvPrt#
$$ifp$ 80C196NT || 80C196NQ
$model(NT)
$$end$
$include (80c196kr.inc)

SLP_IO_CONFIG       set      00Fh
SLPINT_IO_EN        set      010h
PORT3_DRIVE         set      007h
SLP_CBE_BIT         set      002h
SLP_IBE_BIT         set      001h
SLP_OBF_BIT         set      000h
SLP_OBE_INTERRUPT   set      006h
SLP_IBF_INTERRUPT   set      007h
SLP_CBF_INTERRUPT   set      000h
cseg

init_slaveport:
;    slave port configuration:
;         $%TSLP_CON.3$SLP_ENABLE$SLP_DISABLE$
;         $%TSLP_CON.2$SLPL_IS_A1$SLPL_IS_ALE$
$$ifp$ 80C196NT || 80C196NQ || 80C196KT
;         $%TSLP_CON.4$SHARED_MEMORY_MODE$STANDARD_SLAVE_MODE$
$$end$
;         $%TSLP_CON.1$SLPINT_IBE_ENABLE$SLPINT_IBE_DISABLE$
;         $%TSLP_CON.0$SLPINT_OBF_ENABLE$SLPINT_OBF_DISABLE$

     ldb  tmpreg0, #0$$SLP_CON$h
     stb  tmpreg0, slp_con[0]
     ret
$$if$ SLPCON.3
     ldb  tmpreg0, p5_reg[0]
     orb  tmpreg0, #SLP_IO_CONFIG            ;init p5_reg
     stb  tmpreg0, p5_reg[0]
     
     ldb  tmpreg0, p5_dir[0]            ;make all 5.0-5.3 inputs
     orb  tmpreg0, #SLP_IO_CONFIG
      $$if$ SLP_CON.0-1
     CLR_BIT_REG  tmpreg0, 4            ;make SLPINT output
      $$end$
     stb  tmpreg0, p5_dir[0]            ;make all inputs except SLPINT

     ldb  tmpreg0, p5_mode[0]           ;make SLPINT special function
     orb  tmpreg0, #(SLP_IO_CONFIG$%TSLP_CON.0-1$ + SLPINT_IO_EN$$)
     stb  tmpreg0, p5_mode[0]           ;make SLPINT special function
 CLR_BIT p34_drv,PORT3_DRIVE            ;make p3 open drain
     stb  ff_reg, p3_reg[0]             ;init Output Buffer
     stb  zero_reg, slp_cmd[0]          ;init Command register
$$end$
$$if$ int_mask.6
 SET_BIT_REG int_mask,SLP_OBE_INTERRUPT   
$$end$
$$if$ int_mask.7
 SET_BIT_REG int_mask,SLP_IBF_INTERRUPT   
$$end$
$$if$ int_mask1.0
 SET_BIT_REG int_mask1,SLP_CBF_INTERRUPT  
$$end$

$$if$ int_mask.6
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff200Ch
obe_isr_vector:     dcw  LSW slaveport_obe_isr
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 0200Ch
obe_isr_vector:     dcw  slaveport_obe_isr
$$end$
cseg

slaveport_obe_isr:
     pusha
     push tmpreg0

; Data on p3_reg has been read by master.  Buffer is now ready
; for new data

     ldb  tmpreg0, 0           ;place new data here
     stb  tmpreg0, p3_reg[0]
     pop tmpreg0
     popa
     ret

$$end$
$$ifn$ int_mask.6
putchar_slp:
     ldb  tmpreg0, slp_con[0]
     jbs  tmpreg0, SLP_OBF_BIT, putchar_slp
     $$ifp$ 80C196NT || 80C196NQ
     ldb  tmpreg0, 4[sp]
     $$end$
     $$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
     ldb  tmpreg0, 2[sp]
     $$end$
     stb  tmpreg0, p3_reg
     ret
$$end$

$$if$ int_mask.7
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff200Eh
ibf_isr_vector:     dcw  LSW slaveport_ibf_isr
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 0200Eh
ibf_isr_vector:     dcw  slaveport_ibf_isr
$$end$
cseg

slaveport_ibf_isr:
     pusha
     push tmpreg0

; Data on p3_pin has been written by the master.  Data can now
; be read from buffer.

     ldb  tmpreg0, p3_pin[0]              ;new data is read here

; Code to act on new data goes here.

     pop  tmpreg0
     popa
     ret
$$end$
$$ifn$ int_mask.7
getchar_slp:
     ldb  tmpreg0, slp_con[0]
     jbs  tmpreg0, SLP_IBE_BIT, getchar_slp

; Data on p3_pin has been written by the master.  Data can now
; be read from buffer.

     ldbze tmpreg0, p3_pin[0]             ;new data is read here
     ret
$$end$

$$if$ int_mask1.0
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2030h
cbf_isr_vector:     dcw  LSW  slaveport_cbf_isr
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02030h
cbf_isr_vector:     dcw  slaveport_cbf_isr
$$end$
cseg

slaveport_cbf_isr:
     pusha
     push tmpreg0

; Master has just written a new command to slp_cmd.

     ldb  tmpreg0, slp_cmd[0]             ;new command is read here

     ; Code to act on new command goes here.

     pop  tmpreg0
     popa
     ret
$$end$
$$ifn$ int_mask1.0
getcommand_slp:
     ldb  tmpreg0, slp_con[0]
     jbs  tmpreg0, SLP_CBE_BIT, getcommand_slp

; Master has just written a new command to slp_cmd.

     ldb  tmpreg0, slp_cmd[0]             ;new command is returned here
     ret
$$end$

$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2080h
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02080h
$$end$
main_slp:
     ld   sp, #STACK

     call init_slaveport
$$if$ int_mask.6 || int_mask.7 || int_mask1.0
     ei                                   ;global enable interrupts
$$end$
$$ifn$ int_mask.6
     push #041h                           ;send data to master
     call putchar_slp
     add sp, #2
$$end$
$$ifn$ int_mask.7
     call  getchar_slp                    ;receive data from master

; tmpreg0 contains data from master

$$end$
$$ifn$ int_mask1.0
     call getcommand_slp                  ;receive command from master

; tmpreg0  contains command from master

$$end$
     br $
end
##80C196NT ICU#
##80C196NQ ICU#
##80C196KT ICU#
##80C196KQ ICU#
##80C196KR ICU#
##80C196JR ICU#
##80C196JT ICU#
##80C196JQ ICU#
$$ifp$ 80C196NT || 80C196NQ
$model(NT)
$$end$
$include (80c196kr.inc) 
EPAX_INTERRUPT      set       000h
EXTINT_INTERRUPT    set       006h
EPA4_INT            set     08000h
EPA5_INT            set     04000h
EPA6_INT            set     02000h
EPA7_INT            set     01000h
EPA8_INT            set     00800h
EPA9_INT            set     00400h
EPA0_OVR            set     00200h
EPA1_OVR            set     00100h
EPA2_OVR            set     00080h
EPA3_OVR            set     00040h
EPA4_OVR            set     00020h
EPA5_OVR            set     00010h
EPA6_OVR            set     00008h
EPA7_OVR            set     00004h
EPA8_OVR            set     00002h
EPA9_OVR            set     00001h
COMP_CH0            set       008h
COMP_CH1            set       004h
TIMER1_OVR          set       002h
TIMER2_OVR          set       001h
EPAX_TIJMP_MASK     set       01Fh
tmpreg2             set  tmpreg0+2

cseg
init_special_interrupts:
$$if$ int_mask.0
     SET_BIT_REG  int_mask, EPAX_INTERRUPT
$$end$
$$if$ int_mask.1-7

; Enabling of the other direct Interrupts should be generated 
; using the peripheral editor.  The following can be used for 
; template. 
;      
;     orb   int_mask, 0$$INT_MASK$h;
$$end$

$$if$   int_mask1.6
     orb  int_mask1, #EXTINT_INTERRUPT
$$end$
$$if$ int_mask1.0-5

;  Enabling of the other direct Interrupts should be generated 
;  using the peripheral editor.  The following can be used for 
;  template. 
;      
;     orb   int_mask1, 0$$INT_MASK1$h;
$$end$

$$if$ EPA_MASK
;   ****  enabled epa events in epa_mask  ****
     $$if$ EPA_MASK.0
;                  EPA9_OVR
     $$end$
     $$if$ EPA_MASK.1
;                  EPA8_OVR
     $$end$
     $$if$ EPA_MASK.2
;                  EPA7_OVR
     $$end$
     $$if$ EPA_MASK.3
;                  EPA6_OVR
     $$end$
     $$if$ EPA_MASK.4
;                  EPA5_OVR
     $$end$
     $$if$ EPA_MASK.5
;                  EPA4_OVR
     $$end$
     $$if$ EPA_MASK.6
;                  EPA3_OVR
     $$end$
     $$if$ EPA_MASK.7
;                  EPA2_OVR
     $$end$
     $$if$ EPA_MASK.8
;                  EPA1_OVR
     $$end$
     $$if$ EPA_MASK.9
;                  EPA0_OVR
     $$end$
     $$if$ EPA_MASK.10
;                  EPA9_INT
     $$end$
     $$if$ EPA_MASK.11
;                  EPA8_INT
     $$end$
     $$if$ EPA_MASK.12
;                  EPA7_INT
     $$end$
     $$if$ EPA_MASK.13
;                  EPA6_INT
     $$end$
     $$if$ EPA_MASK.14
;                  EPA5_INT
     $$end$
     $$if$ EPA_MASK.15
;                  EPA4_INT
     $$end$
     ld   tmpreg0, #0$$EPA_MASK$h
     st   tmpreg0, epa_mask[0]
$$end$
$$if$ EPA_MASK1

;   ****  enabled epa events in epa_mask1 ****
     $$if$ EPA_MASK1.3
;                  COMP_CH0
     $$end$
     $$if$ EPA_MASK1.2
;                  COMP_CH1
     $$end$
     $$if$ EPA_MASK1.1
;                  TIMER1_OVR
     $$end$
     $$if$ EPA_MASK1.0
;                  TIMER2_OVR
     $$end$
     ld   tmpreg0, #0$$EPA_MASK1$h
     st   tmpreg0, epa_mask1[0]
$$end$
     ret
$$if$ int_mask.0
     $$ifp$ 80C196NT || 80C196NQ

cseg at 0ff2000h
epax_vector:   dcw  LSW epax_isr
     $$end$
     $$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT

cseg at 02000h
epax_vector:   dcw  epax_isr
     $$end$

cseg
epax_isr:
     pusha
     push  tmpreg0
     push  tmpreg2
do_while_more_interrupts:
     ld   tmpreg0,  #base_table_epax
     ld   tmpreg2,  #epaipv
     tijmp tmpreg0, [tmpreg2], #EPAX_TIJMP_MASK

no_more_epax_interrupts:
     pop  tmpreg2
     pop  tmpreg0
     popa
     ret

EPAX_EPA4_INT:
; Insert code for this event here

          $$ifn$ EPA_CON4.6
     ld tmpreg0, epa4_time[0] ;      must read to prevent overrun
          $$end$
          $$if$ EPA_CON4.6 &! EPA_CON4.0 && EPA_CON4.3
     ld tmpreg0, epa4_time[0]
     add tmpreg0, #0$$TIMER_OFFSET4$h
     st tmpreg0, epa4_time[0]
          $$end$
          $$if$ EPA_CON4.6 &! EPA_CON4.3

; Since not re-enabled, no more events will occur unless
; epa_control and epa_time are re-written.
          $$end$
      br  do_while_more_interrupts

EPAX_EPA5_INT:

; Insert code for this event here

          $$ifn$ EPA5_CON.6
     ld  tmpreg0, epa5_time[0] ;      must read to prevent overrun
          $$end$
          $$if$ EPA5_CON.6 &! EPA5_CON.0 && EPA5_CON.3
     ld  tmpreg0, epa5_time[0]
     add tmpreg0, #0$$TIMER_OFFSET5$h
     st  tmpreg0, epa5_time[0]
          $$end$
          $$if$ EPA5_CON.6 &! EPA5_CON.3

; Since not re-enabled, no more events will occur unless
; epa_control and epa_time are re-written.
          $$end$
     br  do_while_more_interrupts

EPAX_EPA6_INT:

; Insert code for this event here
          $$ifn$ EPA6_CON.6
     ld   tmpreg0, epa6_time[0]            ;must read to prevent overrun
          $$end$
          $$if$ EPA6_CON.6 &! EPA6_CON.0 && EPA6_CON.3
     ld   tmpreg0, epa6_time[0]
     add  tmpreg0, #0$$TIMER_OFFSET6$h