📄 196kxa.cod
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$$if$ INT_MASK1.3-4
orb int_mask1, #$%TINT_MASK1.3$TXD_INTERRUPT +$$$%TINT_MASK1.4$ RXD_INTERRUPT$0$;
$$if$ INT_MASK1.4
clr end_rec_buff ;init buffer pointers
clr begin_rec_buff
$$end$
$$if$ INT_MASK1.3
clrb end_trans_buff
clrb begin_trans_buff
$$end$
$$end$
clrb sp_status_image
ret
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2080h
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02080h
$$end$
main_serial:
ld sp, #STACK
call init_serial
$$if$ INT_MASK1.3-4
ei ;global interrupt enable
$$if$ INT_MASK1.4
; The following lines will loop until the letter 'Q' is
; received.
look_for_Q:
call getchar
cmpb tmpreg0, #'Q'
jne look_for_Q
$$end$
$$if$ INT_MASK1.3
; The following line is used to initialize putchar routine,
; so that the first time putchar is called it will send the
; character.
SET_BIT_REG int_pend1, 3 ;set the TXD interrupt bit
SET_BIT sp_status_image, TI_BIT
; Example of sending out buffered data.
push #'H' ;example sequence to send 'Hello'
call putchar
add sp, #2
push #'e'
call putchar
add sp, #2
push #'l'
call putchar
add sp, #2
push #'l'
call putchar
add sp, #2
push #'o'
call putchar
add sp, #2
$$end$
br $
$$end$
$$ifn$ INT_MASK1.3-4
$$if$ P2_MODE.0 && P2_MODE.1
do_forever:
call getchar
push tmpreg0
call putchar
add sp, #2
br do_forever ;transmitt the character received
$$end$
$$if$ P2_MODE.0 &! P2_MODE.1
push #041h ;pass the 'A' character
call putchar ;transmitt a character
add sp, #2
br $
$$end$
$$ifn$ P2_MODE.0 && P2_MODE.1
do_while_not_Q
call getchar
cmpb tmpreg0, #051h ;check for letter 'Q'
bne do_while_not_Q
br $
$$end$
$$end$
end
##80C196NT PM#
##80C196NQ PM#
##80C196KT PM#
##80C196KQ PM#
##80C196KR PM#
##80C196JR PM#
##80C196JT PM#
##80C196JQ PM#
##80C196NT BIU#
##80C196NQ BIU#
##80C196KT BIU#
##80C196KQ BIU#
##80C196KR BIU#
##80C196JR BIU#
##80C196JT BIU#
##80C196JQ BIU#
##80C196NT CPU#
##80C196NQ CPU#
##80C196KT CPU#
##80C196KQ CPU#
##80C196KR CPU#
##80C196JR CPU#
##80C196JT CPU#
##80C196JQ CPU#
##80C196NT CODE#
##80C196NQ CODE#
##80C196KT CODE#
##80C196KQ CODE#
##80C196KR CODE#
##80C196JR CODE#
##80C196JT CODE#
##80C196JQ CODE#
$$ifp$ 80C196NT || 80C196NQ
$include (80c196kr.inc)
cseg at 0ff2018h
$$end$
$$ifp$ 80C196KR || 80C196KQ || 80C196JR || 80C196JQ || 80C196KT || 80C196JT
$include (80c196kr.inc)
cseg at 02018h
$$end$
; **** chip configuration: ****
$$ifn$ CCR0.6-7
; READ_WRITE_PROTECT
$$end$
$$if$ CCR0.6 && CCR0.7
; NO_PROTECT
$$end$
$$if$ CCR0.6 &! CCR0.7
; READ_PROTECT
$$end$
$$ifn$ CCR0.6 && CCR0.7
; WRITE_PROTECT
$$end$
; $%TCCR0.0$POW_DN_ENABLE$POW_DN_DISABLE$
; $%TCCR0.2$WR_BHE$WRL_WRH$
; $%TCCR0.3$ALE_MODE$ADV_MODE$
$$ifn$ CCR1.1
; ZERO_WAIT_STATE
$$end$
$$if$ CCR1.1
$$ifn$ CCR0.4-5
; ONE_WAIT_STATE
$$end$
$$ifn$ CCR0.5 && CCR0.4
; TWO_WAIT_STATE
$$end$
$$if$ CCR0.5 &! CCR0.4
; THREE_WAIT_STATE
$$end$
$$if$ CCR0.5 && CCR0.4
; READY_CONTROLLED
$$end$
$$end$
$$if$ CCR1.2
; $%TCCR0.1$BUSWIDTH_PIN$BUS_WIDTH_8$,
$$end$
$$ifn$ CCR1.2
; $%TCCR0.1$BUS_WIDTH_16$$
$$end$
$$ifp$ 80C196NT || 80C196NQ || 80C196KT
$$if$ CCR1.7
; $%TCCR1.6$STANDARD_BUS$EARLY_ADDRESS$
$$end$
$$ifn$ CCR1.7
; $%TCCR1.6$LONG_RD_WR$STANDARD_ONE_WS$
$$end$
$$if$ CCR1.0
; CCR2_CHAINING_BIT
$$end$
$$end$
$$if$ CCR1.1
; CCR1_WAIT_CONTROL
$$end$
$$if$ CCR1.2
; CCR1_BUS_WIDTH
$$end$
$$if$ CCR1.3
; WDE_ENABLE
$$end$
$$if$ CCR1.0
$$if$ CCR2.2
; REMAP_EPROM
$$end$
$$if$ CCR2.1
; MODE16
$$end$
$$end$
ccr0: dcw 0$$CCR0$h
ccr1: dcw 0$$CCR1$h
$$ifp$ 80C196NT || 80C196NQ
ccr2: dcw 0$$CCR2$h
$$end$
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2080h
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02080h
$$end$
HOLD_CONTROL SET $%tWSR.7$080h$000h$
main_CPU:
ld sp, #STACK
ldb wsr, #HOLD_CONTROL
; **** user code *****
;
; To change wsr use:
; ldb wsr, #HOLD_CONTROL + WINDOW_VALUE
br $
end
##80C196NT WDT#
##80C196NQ WDT#
##80C196KT WDT#
##80C196KQ WDT#
##80C196KR WDT#
##80C196JR WDT#
##80C196JT WDT#
##80C196JQ WDT#
$$ifp$ 80C196NT || 80C196NQ
$model(NT)
$$end$
$include (80c196kr.inc)
CLEAR_WATCHDOG_KEY1 set 01Eh
CLEAR_WATCHDOG_KEY2 set 0E1h
USER_KEY set 0AA55h
cseg
; This routine resets the watchdog timer. The user key
; is used to prevent spurious resetting of the watchdog.
reset_watchdog:
$$ifp$ 80C196NT || 80C196NQ
ld tmpreg0, 4[sp]
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
ld tmpreg0, 2[sp]
$$end$
cmp tmpreg0, #USER_KEY
jne exit_watchdog
ldb watchdog, #CLEAR_WATCHDOG_KEY1
ldb watchdog, #CLEAR_WATCHDOG_KEY2
exit_watchdog:
ret
$$ifp$ 80C196NT || 80C196NQ
cseg at 0ff2080h
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 02080h
$$end$
main_watchdog:
ld sp, #STACK
; **** user code *****
loop_forever_wd:
; **** more user code *****
push #USER_KEY
call reset_watchdog ;should only be called from one
;place in user code
add sp, #2 ;clear stack of parameter
br loop_forever_wd
end
##80C196NT SYNCHSERIAL#
##80C196NQ SYNCHSERIAL#
##80C196KT SYNCHSERIAL#
##80C196KQ SYNCHSERIAL#
##80C196KR SYNCHSERIAL#
##80C196JR SYNCHSERIAL#
##80C196JT SYNCHSERIAL#
##80C196JQ SYNCHSERIAL#
$$ifp$ 80C196NT || 80C196NQ
$model(NT)
$$end$
$include (80c196kr.inc)
SYNC_BAUD_GEN_ENABLE set 080h
SYNC_BAUD_GEN_DISABLE set 000h
SSIO_MASTER set 080h
SSIO_SLAVE set 000h
SSIO_TRANSMITTER set 040h
SSIO_RECEIVER set 000h
SSIO_T_R_BIT_TOGGLE set 020h
SSIO_HANDSHAKE_ENABLE set 010h
SSIO_HANDSHAKE_DISABLE set 000h
SSIO_TRANSFER_ENABLE set 008h
SSIO_AUTO_TRANS_RE_EN set 004h
SSIO_OVERFLOW_FLAG set 001h
SSIO_TRANSCEIVER_STATUS set 000h
SC0_PIN set 004h
SD0_PIN set 005h
SC1_PIN set 006h
SD1_PIN set 007h
SSIO0_INTERRUPT set 001h
SSIO1_INTERRUPT set 002h
cseg
init_ssio$$SSIO_CHANNEL$:
$$if$ SSIO_CON.7 && SSIO_BAUD.7
ldb tmpreg0, #SYNC_BAUD_GEN_ENABLE + 0$$SSIO_BAUD.0-6$h
stb tmpreg0, ssio_baud[0]
$$end$ MASTER AND BAUD_EN
; SSIO CONTROL:
; $%TSSIO_CON.7$SSIO_MASTER$SSIO_SLAVE$ + $%TSSIO_CON.6$SSIO_TRANSMITTER$SSIO_RECEIVER$ +
$$if$ SSIO_CON.5
; SSIO_T_R_BIT_TOGGLE
$$end$
$$if$ SSIO_CON.3
; SSIO_TRANSFER_ENABLE
$$end$
$$if$ SSIO_CON.2
; SSIO_AUTO_TRANS_RE_EN
$$end$
; $%TSSIO_CON.4$SSIO_HANDSHAKE_ENABLE$SSIO_HANDSHAKE_DISABLE$
ldb tmpreg0, #0$$SSIO_CON$h
stb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
$$if$ SSIO_CON.2-7
CLR_BIT p6_reg,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ init reg
$$if$ SSIO_CON.7 &! SSIO_CON.4
CLR_BIT p6_dir,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ output
$$end$
$$ifn$ SSIO_CON.7 || SSIO_CON.4
SET_BIT p6_dir,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ input
$$end$
SET_BIT p6_mode,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ special mode
SET_BIT p6_reg,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ init reg
$$if$ SSIO_CON.6
CLR_BIT p6_dir,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ output
$$end$
$$ifn$ SSIO_CON.6
SET_BIT p6_dir,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ input
$$end$
SET_BIT p6_mode,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ special mode
$$end$
$$ifn$ SSIO_con.0-7
CLR_BIT p6_reg,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ init reg
SET_BIT p6_dir,SC$$SSIO_CHANNEL$_PIN ;SC$$SSIO_CHANNEL$ input
SET_BIT p6_mode,SC$$SSIO_CAHNNEL$_PIN ;SC$$SSIO_CHANNEL$ special mode
SET_BIT p6_reg,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ init reg
SET_BIT p6_dir,SD$$SSIO_CHANNEL$_PIN ;SD$$SSIO_CHANNEL$ input
SET_BIT p6_mode,SD$$SSIO_CAHNNEL$_PIN ;SD$$SSIO_CHANNEL$ special mode
$$end$
$$if$ SSIO_INTERRUPT
SET_BIT_REG int_mask1,SSIO$$SSIO_CHANNEL$_INTERRUPT ;unmask the interrupt
$$end$
ret
$$if$ SSIO_INTERRUPT
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
cseg at 2032h + 2 * $$SSIO_CHANNEL$
ssio$$SSIO_CHANNEL$_vector: dcw ssio$$SSIO_CHANNEL$_isr
$$end$
$$ifp$ 80C196NT || 80C196NQ
cseg at 0FF2038h + 2 * $$SSIO_CHANNEL$
ssio$$SSIO_CHANNEL$_vector: dcw LSW ssio$$SSIO_CHANNEL$_isr
$$end$
cseg
ssio$$SSIO_CHANNEL$_isr:
pusha
push tmpreg0
$$if$ SSIO_CON.6
; SSIO transmitt interrupt service routine
$$if$ SSIO_CON.2
$$ifn$ SSIO_CON.2
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
orb tmpreg0, #SSIO_TRANSFER_ENABLE
stb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
$$end$
; **** NEXT BYTE TO SEND GOES HERE ***
ldb tmpreg0, #0 ; new data
stb tmpreg0, ssio$$SSIO_CHANNEL$_buf[0]
; ****** check for overflow ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_OVERFLOW_FLAG, no_ov$$SSIO_CHANNEL$_error
; User code for overflow during transmit
no_ov$$SSIO_CHANNEL$_error:
$$end$
$$end$
$$ifn$ SSIO_CON.6
;********** code to handle received character ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_buf[0]
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_OVERFLOW_FLAG, no_ov$$SSIO_CHANNEL$_error
; User code for overflow during receive
no_ov$$SSIO_CHANNEL$_error:
$$ifn$ SSIO_CON.2
; **** re enable a transfer ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
orb tmpreg0, #SSIO_TRANSFER_ENABLE
stb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
$$end$
$$end$
pop tmpreg0
popa
ret
$$end$
$$ifn$ SSIO_INTERRUPT
$$if$ SSIO_CON.6
ssio$$SSIO_CHANNEL$_putchar:
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_TRANSCEIVER_STATUS, ssio$$SSIO_CHANNEL$_putchar
; ****** check for overflow ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_OVERFLOW_FLAG, no_ov$$SSIO_CHANNEL$_error
; User code for overflow during transmit
no_ov$$SSIO_CHANNEL$_error:
$$ifn$ SSIO_CON.2
; **** re enable a transfer ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
orb tmpreg0, #SSIO_TRANSFER_ENABLE
stb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
$$end$
$$ifp$ 80C196NT || 80C196NQ
ld tmpreg0, 4[sp]
$$end$
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
ld tmpreg0, 2[sp]
$$end$
stb tmpreg0, ssio$$SSIO_CHANNEL$_buf[0]
ret
$$end$
$$ifn$ SSIO_CON.6
ssio$$SSIO_CHANNEL$_getchar:
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_TRANSCEIVER_STATUS, ssio$$SSIO_CHANNEL$_getchar
; ****** check for overflow ****
ldb tmpreg0, ssio$$SSIO_CHANNEL$_con[0]
jbc tmpreg0, SSIO_OVERFLOW_FLAG, no_ov$$SSIO_CHANNEL$_error_rec
; User code for overflow during transmit
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