196kxc.cod

mcs51,2051,x86系列MCU

     $$ifp$ 80C196NT || 80C196NQ
#define   CCR2_CHAINING_BIT  0x01
#define   CCR2_RESERVED      0xF8
#define   REMAP_EPROM        0x04
#define   NO_EPROM_REMAP     0x00
#define   MODE16             0x02
#define   MODE24             0x00
     $$end$
$$end$
static const unsigned int CCB[] =
          { 0x2000 |
$$ifn$ CCR0.6-7
            READ_WRITE_PROTECT |
$$end$
$$if$ CCR0.6 && CCR0.7
            NO_PROTECT |
$$end$
$$if$ CCR0.6 &! CCR0.7
            READ_PROTECT |
$$end$
$$ifn$ CCR0.6 && CCR0.7
            WRITE_PROTECT |
$$end$
            $%TCCR0.0$POW_DN_ENABLE$POW_DN_DISABLE$ |
            $%TCCR0.2$WR_BHE$WRL_WRH$ |
            $%TCCR0.3$ALE_MODE$ADV_MODE$ |
$$ifn$ CCR1.1
            ZERO_WAIT_STATE |
$$end$
$$if$ CCR1.1
     $$ifn$ CCR0.4-5
            ONE_WAIT_STATE |
     $$end$
     $$ifn$ CCR0.5 && CCR0.4
            TWO_WAIT_STATE |
     $$end$
     $$if$ CCR0.5 &! CCR0.4
            THREE_WAIT_STATE |
     $$end$
     $$if$ CCR0.5 && CCR0.4
            READY_CONTROLLED |
     $$end$
$$end$
$$if$ CCR1.2
            $%TCCR0.1$BUSWIDTH_PIN$BUS_WIDTH_8$,
$$end$
$$ifn$ CCR1.2
            $%TCCR0.1$BUS_WIDTH_16$0$,
$$end$
            0x2000 | 
$$ifp$ 80C196NT || 80C196NQ || 80C196KT
     $$if$ CCR1.7
            $%TCCR1.6$STANDARD_BUS$EARLY_ADDRESS$ |
     $$end$
     $$ifn$ CCR1.7
            $%TCCR1.6$LONG_RD_WR$STANDARD_ONE_WS$ |
     $$end$
     $$if$ CCR1.0
            CCR2_CHAINING_BIT |
     $$end$
$$end$
$$if$ CCR1.1
            CCR1_WAIT_CONTROL |
$$end$
$$if$ CCR1.2
            CCR1_BUS_WIDTH |
$$end$
$$if$ CCR1.3
            WDE_ENABLE |
$$end$
            CCR1_RESERVED$%TCCR1.0$,$};$
$$if$ CCR1.0
            0x2000 |
            $%TCCR.2$REMAP_EPROM$NO_EPROM_REMAP$ |
     $$if$ CCR2.1
            $%TCCR2.1$MODE16$MODE24$ |
     $$end$
            CCR2_RESERVED};
$$end$
$$ifp$ 80C196NT || 80C196NQ 
#pragma locate (CCB=0x00FF2018)
$$end$
$$ifp$ 80C196KR || 80C196KQ || 80C196JR || 80C196JQ || 80C196KT || 80C196JT
#pragma locate (CCB=0x2018)
$$end$

#define   HOLD_CONTROL   $%tWSR.7$0x80$0x00$

void main(void)
{
 wsr = HOLD_CONTROL;
/*   Users code   */

/*  To change wsr use:

 wsr = HOLD_CONTROL | WINDOW_VALUE;
*/ 
 while(1);
} 
##80C196NT WDT#
##80C196NQ WDT#
##80C196KT WDT#
##80C196KQ WDT#
##80C196KR WDT#
##80C196JR WDT#
##80C196JT WDT#
##80C196JQ WDT#
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
#pragma model(KR)
$$end$
$$ifp$ 80C196NT || 80C196NQ
#pragma model(NT)
$$end$
#include <80c196kr.h>
#define   CLEAR_WATCHDOG_KEY1   0x1E
#define   CLEAR_WATCHDOG_KEY2   0xE1
#define   USER_KEY              0xAA55

/*   This routine resets the watchdog timer.  The user key
     is used to prevent spurious resetting of the watchdog.
*/

void reset_watchdog(unsigned int key)
{
 if(key == USER_KEY)
     {
     watchdog = CLEAR_WATCHDOG_KEY1;
no_optimize_label:
     watchdog = CLEAR_WATCHDOG_KEY2;
     }
}
void main(void)
{
/*    user code   */
while(1)
     {
/*        more user code    */


     reset_watchdog(USER_KEY); /* should only be in one place in
                                  the code */
     }
}
##80C196NT SYNCHSERIAL#
##80C196NQ SYNCHSERIAL#
##80C196KT SYNCHSERIAL#
##80C196KQ SYNCHSERIAL#
##80C196KR SYNCHSERIAL#
##80C196JR SYNCHSERIAL#
##80C196JT SYNCHSERIAL#
##80C196JQ SYNCHSERIAL#
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
#pragma model(KR)
$$end$
$$ifp$ 80C196NT || 80C196NQ
#pragma model(NT)
$$end$
#include <80c196kr.h>
#define   SYNC_BAUD_GEN_ENABLE     0x80
#define   SYNC_BAUD_GEN_DISABLE    0x00
#define   SSIO_MASTER              0x80
#define   SSIO_SLAVE               0x00
#define   SSIO_TRANSMITTER         0x40
#define   SSIO_RECEIVER            0x00
#define   SSIO_T_R_BIT_TOGGLE      0x20
#define   SSIO_HANDSHAKE_ENABLE    0x10
#define   SSIO_HANDSHAKE_DISABLE   0x00
#define   SSIO_TRANSFER_ENABLE     0x08
#define   SSIO_AUTO_TRANS_RE_EN    0x04
#define   SSIO_OVERFLOW_FLAG       0x01
#define   SSIO_TRANSCEIVER_STATUS  0x00
#define   SC0_PIN                  0x04
#define   SD0_PIN                  0x05
#define   SC1_PIN                  0x06
#define   SD1_PIN                  0x07
#define   SSIO0_INTERRUPT          0x01
#define   SSIO1_INTERRUPT          0x02

void init_ssio$$SSIO_CHANNEL$()
{
$$if$ SSIO_CON.7 && SSIO_BAUD.7
 ssio_baud = SYNC_BAUD_GEN_ENABLE | 0x$$SSIO_BAUD.0-6$;
$$end$         /*  MASTER AND BAUD_EN  */
 ssio$$SSIO_CHANNEL$_con = $%TSSIO_CON.7$SSIO_MASTER$SSIO_SLAVE$ | $%TSSIO_CON.6$SSIO_TRANSMITTER$SSIO_RECEIVER$ |
$$if$  SSIO_CON.5
                SSIO_T_R_BIT_TOGGLE |
$$end$
$$if$  SSIO_CON.3
                SSIO_TRANSFER_ENABLE |
$$end$
$$if$  SSIO_CON.2
                SSIO_AUTO_TRANS_RE_EN |
$$end$
                $%TSSIO_CON.4$SSIO_HANDSHAKE_ENABLE$SSIO_HANDSHAKE_DISABLE$;

$$if$  SSIO_CON.2-7
 clrbit(p6_reg,SC$$SSIO_CHANNEL$_PIN);    /*  SC$$SSIO_CHANNEL$ init reg  */
     $$if$ SSIO_CON.7 &! SSIO_CON.4
 clrbit(p6_dir,SC$$SSIO_CHANNEL$_PIN);    /*  SC$$SSIO_CHANNEL$ output  */
     $$end$
     $$ifn$ SSIO_CON.7 || SSIO_CON.4
 setbit(p6_dir,SC$$SSIO_CHANNEL$_PIN);    /*  SC$$SSIO_CHANNEL$ input  */
     $$end$
 setbit(p6_mode,SC$$SSIO_CHANNEL$_PIN);   /*  SC$$SSIO_CHANNEL$ special mode  */
 setbit(p6_reg,SD$$SSIO_CHANNEL$_PIN);    /*  SD$$SSIO_CHANNEL$ init reg  */
     $$if$  SSIO_CON.6
 clrbit(p6_dir,SD$$SSIO_CHANNEL$_PIN);    /*  SD$$SSIO_CHANNEL$ transmitter */
     $$end$
     $$ifn$  SSIO_CON.6
 setbit(p6_dir,SD$$SSIO_CHANNEL$_PIN);    /*  SD$$SSIO_CHANNEL$ receiver  */
     $$end$
 setbit(p6_mode,SD$$SSIO_CHANNEL$_PIN);   /*  SD$$SSIO_CHANNEL$ special mode  */
$$end$
$$ifn$  SSIO_CON.0-7
 setbit(p6_reg, SC$$SSIO_CHANNEL$_PIN);   /* SC$$SSIO_CHANNEL$ init reg */
 setbit(p6_dir, SC$$SSIO_CHANNEL$_PIN);   /* SC$$SSIO_CHANNEL$ input    */
 setbit(p6_mode, SC$$SSIO_CHANNEL$_PIN);  /* SC$$SSIO_CHANNEL$ special mode */
 setbit(p6_reg, SD$$SSIO_CHANNEL$_PIN);   /* SD$$SSIO_CHANNEL$ init reg */
 setbit(p6_dir, SD$$SSIO_CHANNEL$_PIN);   /* SD$$SSIO_CHANNEL$ input    */
 setbit(p6_mode, SD$$SSIO_CHANNEL$_PIN);  /* SD$$SSIO_CHANNEL$ special mode */
$$end$ 
$$if$ SSIO_INTERRUPT

 setbit(int_mask1,SSIO$$SSIO_CHANNEL$_INTERRUPT);  /*  un-mask the interrupt  */
$$end$
}
$$if$ SSIO_INTERRUPT

     $$if$ (SSIO_CHANNEL == 0)
#pragma interrupt(ssio$$SSIO_CHANNEL$_isr = 25)
     $$end$
     $$if$ (SSIO_CHANNEL == 1)
#pragma interrupt(ssio$$SSIO_CHANNEL$_isr = 26)
     $$end$
void ssio$$SSIO_CHANNEL$_isr(void)
{
     $$if$  SSIO_CON.6
/*   SSIO transmitt interrupt service routine  */
          $$if$ SSIO_CON.2
               $$ifn$ SSIO_CON.2
 ssio$$SSIO_CHANNEL$_con |= SSIO_TRANSFER_ENABLE;  /*  enable send  */
               $$end$
 ssio$$SSIO_CHANNEL$_buf = 0;  /*  next byte to send  */
 if(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_OVERFLOW_FLAG))
     {
/*   User code for overflow during transmit  */
     }
          $$end$
     $$end$
     $$ifn$  SSIO_CON.6
unsigned char rec_byte;
 rec_byte = ssio$$SSIO_CHANNEL$_buf;
 if(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_OVERFLOW_FLAG))
     {
/*   User code for overflow during receive  */
     }
           $$ifn$ SSIO_CON.2
 ssio$$SSIO_CHANNEL$_con |= SSIO_TRANSFER_ENABLE;  /*  enable send  */
           $$end$
     $$end$
}
$$end$
$$ifn$ SSIO_INTERRUPT
     $$if$  SSIO_CON.6
void ssio$$SSIO_CHANNEL$_putchar(unsigned char send_byte)
{
 while(!(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_TRANSCEIVER_STATUS)));
 if(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_OVERFLOW_FLAG))
     {
/*   User code for overflow during transmit  */
     }
           $$ifn$ SSIO_CON.2
 ssio$$SSIO_CHANNEL$_con |= SSIO_TRANSFER_ENABLE;  /*  enable transfer */
           $$end$
 ssio$$SSIO_CHANNEL$_buf = send_byte;  /*  next byte to send  */
}
     $$end$
     $$ifn$  SSIO_CON.6

unsigned char ssio$$SSIO_CHANNEL$_getchar(void)
{
 while(!(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_TRANSCEIVER_STATUS)));
 if(checkbit(ssio$$SSIO_CHANNEL$_con, SSIO_OVERFLOW_FLAG))
     {
/*   User code for overflow during receive  */
     }
           $$ifn$ SSIO_CON.2
 ssio$$SSIO_CHANNEL$_con |= SSIO_TRANSFER_ENABLE;  /*  enable transfer  */
           $$end$
 return ssio$$SSIO_CHANNEL$_buf;
}
     $$end$
$$end$

void main(void)
{
 init_ssio$$SSIO_CHANNEL$();
$$if$ SSIO_INTERRUPT
 enable();
     $$if$  SSIO_CON.6
           $$ifn$ SSIO_CON.4
 ssio$$SSIO_CHANNEL$_con |= SSIO_TRANSFER_ENABLE;  /*  enable send  */
           $$end$
 ssio$$SSIO_CHANNEL$_buf = 0;  /*  start the transmissions  */
     $$end$
 while(1);    /*   wait around for interrupt   */
$$end$
$$ifn$ SSIO_INTERRUPT
     $$if$  SSIO_CON.6
 ssio$$SSIO_CHANNEL$_buf = 0;  /*  start the transmissions  */
 while(1)
    ssio$$SSIO_CHANNEL$_putchar('A');  /*  send a 'A' forever  */
     $$end$
     $$ifn$  SSIO_CON.6
 while(ssio$$SSIO_CHANNEL$_getchar() == 'A');  /*  wait while 'A' received  */
     $$end$
$$end$
}
##80C196NT SlvPrt#
##80C196NQ SlvPrt#
##80C196KT SlvPrt#
##80C196KQ SlvPrt#
##80C196KR SlvPrt#
##80C196JR SlvPrt#
##80C196JT SlvPrt#
##80C196JQ SlvPrt#
$$ifp$ 80C196KT || 80C196KQ || 80C196KR || 80C196JR || 80C196JQ || 80C196JT
#pragma model(KR)
$$end$
$$ifp$ 80C196NT || 80C196NQ
#pragma model(NT)
$$end$
#include <80c196kr.h>
#define   SLP_ENABLE          0x08
#define   SLP_DISABLE         0x00
#define   SLPL_IS_ALE         0x00
#define   SLPL_IS_A1          0x04
$$ifp$ 80C196NT || 80C196NQ || 80C196KT
#define   SHARED_MEMORY_MODE  0x10
#define   STANDARD_SLAVE_MODE 0x00
$$end$
#define   SLPINT_IBE_ENABLE   0x02
#define   SLPINT_IBE_DISABLE  0x00
#define   SLPINT_OBF_ENABLE   0x01
#define   SLPINT_OBF_DISABLE  0x00
#define   SLPL_IS_ALE         0x00
#define   SLP_IO_CONFIG       0x0F
#define   SLPINT_IO_EN        0x10
#define   PORT3_DRIVE         0x07
#define   SLP_CBE_BIT         0x02
#define   SLP_IBE_BIT         0x01
#define   SLP_OBF_BIT         0x00
#define   SLP_OBE_INTERRUPT   0x06
#define   SLP_IBF_INTERRUPT   0x07
#define   SLP_CBF_INTERRUPT   0x00

void init_slaveport(void)
{
 slp_con = $%TSLP_CON.3$SLP_ENABLE$SLP_DISABLE$ | $%TSLP_CON.2$SLPL_IS_A1$SLPL_IS_ALE$ |
$$ifp$ 80C196NT || 80C196NQ || 80C196KT
           $%TSLP_CON.4$SHARED_MEMORY_MODE$STANDARD_SLAVE_MODE$ |
$$end$
           $%TSLP_CON.1$SLPINT_IBE_ENABLE$SLPINT_IBE_DISABLE$ | $%TSLP_CON.0$SLPINT_OBF_ENABLE$SLPINT_OBF_DISABLE$;
$$if$ SLP_CON.3
 p5_reg |= SLP_IO_CONFIG;       /*  Init p5_reg to all 1's */
 p5_dir |= SLP_IO_CONFIG;       /*  Make 5.0 - 5.3  inputs */
     $$if$ SLP_CON.0-1
 clrbit(p5_dir, 4);      /*  make slpint output  */
     $$end$    
 p5_mode |= SLP_IO_CONFIG$%TSLP_CON.0-1$ | SLPINT_IO_EN$$;        /*  Select special function  */
 clrbit(p34_drv,PORT3_DRIVE);  /*  Make p3 open drain  */
 p3_reg = 0xFF;     /*   Init Output Buffer  */
 slp_cmd = 0;       /*   Init Command register  */
$$end$
$$if$ int_mask.6
 setbit(int_mask,SLP_OBE_INTERRUPT);
$$end$
$$if$ int_mask.7
 setbit(int_mask,SLP_IBF_INTERRUPT);
$$end$
$$if$ int_mask1.0
 setbit(int_mask1,SLP_CBF_INTERRUPT);
$$end$
}

$$if$ int_mask.6
#pragma interrupt(slaveport_obe_isr=6)
void slaveport_obe_isr(void)
{
/*   Data on p3_reg has been read by master.  Buffer is now ready
     for new data   */
 p3_reg = 0;  /*  place new data here  */
}
$$end$
$$ifn$ int_mask.6
void putchar_slp(unsigned char new_data)
{
 while(checkbit(slp_con,SLP_OBF_BIT));
 p3_reg = new_data;
}
$$end$

$$if$ int_mask.7
#pragma interrupt(slaveport_ibf_isr=7)
void slaveport_ibf_isr(void)
{
static unsigned char new_data;
/*   Data on p3_pin has been written by the master.  Data can now
     be read from buffer   */
 new_data = p3_pin;  /*  new data is read here  */

/*   Code to act on new data goes here.      */
}
$$end$
$$ifn$ int_mask.7
unsigned char getchar_slp(void)
{
 while(checkbit(slp_con,SLP_IBE_BIT));
/*   Data on p3_pin has been written by the master.  Data can now
     be read from buffer   */
 return(p3_pin);  /*  new data is read here  */
}
$$end$

$$if$ int_mask1.0
#pragma interrupt(slaveport_cbf_isr=24)
void slaveport_cbf_isr(void)
{
static unsigned char new_command;
/*   Master has just written a new command to slp_cmd.   */
 new_command = slp_cmd;  /*  new command is read here  */

/*   Code to act on new command goes here.      */
}
$$end$
$$ifn$ int_mask1.0
unsigned char getcommand_slp(void)
{
 while(checkbit(slp_con,SLP_CBE_BIT));
/*   Master has just written a new command to slp_cmd.   */
 return(slp_cmd);  /*  new command is returned here  */
}
$$end$

void main(void)
{
$$ifn$ int_mask.6 |! int_mask.7 |! int_mask1.0
unsigned char data,command;
$$end$

 init_slaveport();
$$if$ int_mask.6 || int_mask.7 || int_mask1.0
 enable();
$$end$
$$ifn$ int_mask.6
 putchar_slp(data);   /*  send data to master  */
$$end$
$$ifn$ int_mask.7
 data = getchar_slp();   /*  receive data from master  */
$$end$