196c.cod

mcs51,2051,x86系列MCU

*/

typedef struct SingleTran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc;
                             void  *ptsdst;
                             int   :16; /* unused */
                             } SingleTran_ptscb;

/* 
*  This locates the PTS Single mode control block.
*  This control block may be located at any quad-word 
*  boundary in register space.
*/

SingleTran_ptscb Single_CB_$$PTS_VECTOR$;
$$ifp$ 80C196KC 
#pragma locate(Single_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x180$)
$$end$
$$ifp$ 80C196KD 
#pragma locate(Single_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x380$)
$$end$
/*
*  The PTS vector must contain the address of the PTS control
*  block.
*/

#pragma pts(Single_CB_$$PTS_VECTOR$=0x$$PTS_VECTOR$)

/*
*  The Interrupt vector must contain the address of the
*  end-of-pts interrupt service routine.
*/

#pragma interrupt(End_of_PTS=@@INT_VECTOR@)
   
/*
*  The following code is an example of a PTS control block
*  initialization sequence.
*/

void Init_SingleTrans_PTS_$$PTS_VECTOR$(void)
{
    Single_CB_$$PTS_VECTOR$.ptscount = 0x@@PTSCOUNT@;
    Single_CB_$$PTS_VECTOR$.ptssrc   = (void *)0x@@PTSSRC@;
    Single_CB_$$PTS_VECTOR$.ptsdst   = (void *)0x@@PTSDST@;
    Single_CB_$$PTS_VECTOR$.ptscon   = $%cPTSCON$;
}

/*
*  When the PTS cycle is finished it will generate an end-of-pts
*  interrupt.
*/

void End_of_PTS(void)
{
  /* User Code */
}

void main_pts_single(void)
{
  Init_SingleTrans_PTS_$$PTS_VECTOR$();
  while(1);
}
##80C196KC PTS_Block#
##80C196KD PTS_Block#
#pragma model(kc)
#include <80c196kd.h>

/* 
*  Create typedef template for the block transfer control
*  block.
*/

typedef struct BlockTran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc;
                             void  *ptsdst;
                             unsigned char ptsblock;
                             unsigned char unused;
                         } BlockTran_ptscb;

/* 
*  This locates the PTS Block mode control block.
*  This control block may be located at any quad-word 
*  boundary in register space.
*/

BlockTran_ptscb Block_CB_$$PTS_VECTOR$;
$$ifp$ 80C196KC 
#pragma locate(Block_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x180$)
$$end$
$$ifp$ 80C196KD 
#pragma locate(Block_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x380$)
$$end$

/*
*  The PTS vector must contain the address of the PTS control
*  block.
*/

#pragma pts(Block_CB_$$PTS_VECTOR$=0x$$PTS_VECTOR$)

/*
*  The Interrupt vector must contain the address of the
*  end-of-pts interrupt service routine.
*/

#pragma interrupt(End_of_PTS=@@INT_VECTOR@)
   
/*
*  The following code is an example of a PTS control block
*  initialization sequence.
*/

void Init_BlockTrans_PTS_$$PTS_VECTOR$(void)
{
    Block_CB_$$PTS_VECTOR$.ptscount = 0x@@PTSCOUNT@;
    Block_CB_$$PTS_VECTOR$.ptssrc   = (void *)0x@@PTSSRC@;
    Block_CB_$$PTS_VECTOR$.ptsdst   = (void *)0x@@PTSDST@;
    Block_CB_$$PTS_VECTOR$.ptscon   = 0x@@PTSCON@;
    Block_CB_$$PTS_VECTOR$.ptsblock = 0x@@PTSBLOCK@;
}

/*
*  When the PTS cycle is finished it will generate an end-of-pts
*  interrupt.
*/

void End_of_PTS(void)
{
  /* User Code */
}

void main_pts_block(void)
{
  Init_BlockTrans_PTS_$$PTS_VECTOR$();
  while(1);
}
##80C196KC PTS_AD#
##80C196KD PTS_AD#
#pragma model(kc)
#include <80c196kd.h>

/* 
*  Create typedef template for the A/D Scan Mode control
*  block.
*/

typedef struct ADscanTran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc_dst;
                             void  *ptsreg;
                             unsigned char ptsblock;
                             int    :16;   /* Unused */
                         } ADscanTran_ptscb;

/* 
*  This locates the AtoD scan mode control block.
*  This control block may be located at any quad-word 
*  boundary in register space.
*/

ADscanTran_ptscb ADscan_CB_$$PTS_VECTOR$;
$$ifp$ 80C196KC 
#pragma locate(ADscan_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x180$)
$$end$
$$ifp$ 80C196KD 
#pragma locate(ADscan_CB_$$PTS_VECTOR$=$%XPTS_VECTOR * 8 + 0x380$)
$$end$

/*
*  The PTS vector must contain the address of the PTS control
*  block.
*/

#pragma pts(ADscan_CB_$$PTS_VECTOR$=0x$$PTS_VECTOR$)

/*
*  The Interrupt vector must contain the address of the
*  end-of-pts interrupt service routine.
*/

#pragma interrupt(End_of_PTS=@@INT_VECTOR@)
   
/*
* This allows the AD table of commands and results to be
* relocatable in the data segment.  This table can also
* reside in register space.
*/

struct {
     unsigned int command;
     unsigned int result;
} @@PTS_AD_TBL@[@@PTSCOUNT@+1];

/*
*  The following code is an example of a PTS control block
*  initialization sequence.
*/

void Init_ADscanTrans_PTS_$$PTS_VECTOR$(void)
{
  int i;
    disable();          /* Disable all Interrupts */
    disable_pts();      /* Disable the PTS Interrupts */
    
    ADscan_CB_$$PTS_VECTOR$.ptscount   = 0x@@PTSCOUNT@;
    ADscan_CB_$$PTS_VECTOR$.ptssrc_dst = (void *)@@PTS_AD_TBL@;
    ADscan_CB_$$PTS_VECTOR$.ptsreg     = (void *)&ad_result;  /* Address of AD_RESULT */
    ADscan_CB_$$PTS_VECTOR$.ptscon     = 0x$$PTSCON$;

/*
* The following code will load a table of AD commands starting
* at the location specified by @@PTS_AD_TBL@. The commands
* will start AD conversions on AD Channels 0 - @@PTSCOUNT@.
*/

    for(i=0; i < @@PTSCOUNT@; i++)
        @@PTS_AD_TBL@[i].command = 0x9 + (i & 0x07);

/* Stop Doing A/D scans after @@PTSCOUNT@ */

  @@PTS_AD_TBL@[i].command = 0;

/*
* To enable PTS the A/D interrupt INT_MASK.1 and PTSSEL.1
* must be set. Checking the 'Enable the PTS Interrupt' box 
* will set these bits clearing the box will clear these bits.
*/

  _$%tint_mask.1$Set$Clr$SFR_bit (int_mask, 1);
  _$%tptssel.1$Set$Clr$SFR_bit (ptssel, 1);
  _WriteSFR (ad_command, 0x08);  /* Start Channel 0 now */

/* Enable Interrupts */

  enable();
  enable_pts();
}

/*
*  When the PTS cycle is finished it will generate an end-of-pts
*  interrupt.
*/

void End_of_PTS(void)
{
  /*
     User code - called when scan is finished
     user needs to reinitialize the A/D PTS control block
     if desired.
  */
}

void main_pts_ad(void)
{
  Init_ADscanTrans_PTS_$$PTS_VECTOR$();
  while(1);
}
##80C196KC PTS_HSO#
##80C196KD PTS_HSO#
#pragma model(kc)
#include <80c196kd.h>

/* 
*  Create typedef template for the block transfer control
*  block.
*/

typedef struct HSO_Tran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc;
                             int    :16;        /* unused */
                             unsigned char ptsblock;
                             unsigned char unused;
                         } HSO_Tran_ptscb;

/*
* This locates the PTS HSO mode control block at location
* 50H.  This control block may be located at any quad-word 
* boundary in register space. 
*/

HSO_Tran_ptscb HSO_CB_$$PTS_VECTOR$;
#pragma locate(HSO_CB_$$PTS_VECTOR$=0x50)

/*
*  The PTS vector must contain the address of the PTS control
*  block.
*/

#pragma pts(HSO_CB_$$PTS_VECTOR$=0x$$PTS_VECTOR$)

/*
*  The Interrupt vector must contain the address of the
*  end-of-pts interrupt service routine.
*/

#pragma interrupt(End_of_PTS=@@INT_VECTOR@)

/* Create the HSO table of commands */

struct HSO_Command_tbl_s    {
    unsigned int command;
    unsigned int time;
} @@PTS_SRC_TBL@[8];

void Init_HSO_Trans_PTS_$$PTS_VECTOR$(void)
{
    HSO_CB_$$PTS_VECTOR$.ptscount = 0x0@@PTSCOUNT@;
    HSO_CB_$$PTS_VECTOR$.ptssrc   = (void *)@@PTS_SRC_TBL@;
    HSO_CB_$$PTS_VECTOR$.ptscon   = 0x$$PTSCON$;
    HSO_CB_$$PTS_VECTOR$.ptsblock = 0x0@@PTSBLOCK@;
}

/*
* The following code is an example of an HSO table of
* commands. The table fills the CAM and the holding
* register.  The location of the table is specified by
* @@PTS_SRC_TBL@
*/

void Load_HSO_Cmd_Tbl(void)
{
/*
*   @@PTS_SRC_TBL@[0].command = <enter hso command 0>;
*   @@PTS_SRC_TBL@[0].time    = <enter time 0>;
*   @@PTS_SRC_TBL@[1].command = <enter hso command 1>;
*   @@PTS_SRC_TBL@[1].time    = <enter time 1>;
*   @@PTS_SRC_TBL@[2].command = <enter hso command 2>;
*   @@PTS_SRC_TBL@[2].time    = <enter time 2>;
*   @@PTS_SRC_TBL@[3].command = <enter hso command 3>;
*   @@PTS_SRC_TBL@[3].time    = <enter time 3>;
*   @@PTS_SRC_TBL@[4].command = <enter hso command 4>;
*   @@PTS_SRC_TBL@[4].time    = <enter time 4>;
*   @@PTS_SRC_TBL@[5].command = <enter hso command 5>;
*   @@PTS_SRC_TBL@[5].time    = <enter time 5>;
*   @@PTS_SRC_TBL@[6].command = <enter hso command 6>;
*   @@PTS_SRC_TBL@[6].time    = <enter time 6>;
*   @@PTS_SRC_TBL@[7].command = <enter hso command 7>;
*   @@PTS_SRC_TBL@[7].time    = <enter time 7>;
*/
}

/*
*  When the PTS cycle is finished it will generate an end-of-pts
*  interrupt.
*/

void End_of_PTS(void)
{
  /* User Code */
}

void main_pts_hso(void)
{
  Init_HSO_Trans_PTS_$$PTS_VECTOR$();
  while(1);
}
##80C196KC PTS_HSI#
##80C196KD PTS_HSI#
#pragma model(kc)
#include <80c196kd.h>

/* 
*  Create typedef template for the HSI transfer control
*  block.
*/

typedef struct HSI_Tran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptsdst;
                             int    :16;        /* unused */
                             unsigned char ptsblock;
                             unsigned char unused;
                         } HSI_Tran_ptscb;

/*
* This locates the PTS HSI mode control block at location
* 50H.  This control block may be located at any quad-word 
* boundary in register space. 
*/

HSI_Tran_ptscb HSI_CB_$$PTS_VECTOR$;
#pragma locate(HSI_CB_$$PTS_VECTOR$=0x50)

/*
*  The PTS vector must contain the address of the PTS control
*  block.
*/

#pragma pts(HSI_CB_$$PTS_VECTOR$=0x$$PTS_VECTOR$)

/*
*  The Interrupt vector must contain the address of the
*  end-of-pts interrupt service routine.
*/

#pragma interrupt(End_of_PTS=@@INT_VECTOR@)

/*
* This allows the HSI FIFO table to be relocatable in the data
* segment.  This table can also reside in register space.
*/

unsigned int @@PTS_DST_TBL@[16];

/*
* The following code is an example of a PTS control block
* initialization sequence.
*/

void Init_HSI_Trans_PTS_$$PTS_VECTOR$(void)
{
    HSI_CB_$$PTS_VECTOR$.ptscount = 0x0@@PTSCOUNT@;
    HSI_CB_$$PTS_VECTOR$.ptsdst   = (void *)@@PTS_DST_TBL@;
    HSI_CB_$$PTS_VECTOR$.ptscon   = 0x$$PTSCON$;
    HSI_CB_$$PTS_VECTOR$.ptsblock = 0x0@@PTSBLOCK@;
}

/*
*  When the PTS cycle is finished it will generate an end-of-pts
*  interrupt.
*/

void End_of_PTS(void)
{
  /* User Code */
}

void main_pts_hsi(void)
{
  Init_HSI_Trans_PTS_$$PTS_VECTOR$();
  while(1);
}
##80C194 IO#
##80C198 IO#
##80C196KB IO#
##80C196KC IO#
##80C196KD IO#
$$ifp$ 80C198 || 80C194 || 80C196KB
#pragma model(kb)
$$end$
$$ifp$ 80C196KC || 80C196KD
#pragma model(kc)
$$end$
#include <80c196kd.h>

$$ifp$ 80C196KC || 80C196KD
#define    PWM1_ENABLE              2
#define    PWM2_ENABLE              3
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
#define    BREQ_HOLD_HOLDA_ENABLE   7
$$end$
#define    TXD_ENABLE               5
#define    RXD_ENABLE               3
#define    EXTINT_DISABLE           1  
#define    T2CLK_SRC                7
#define    T2RST_SRC                5
#define    PWM0_ENABLE              1 
#define    T2UPDN_ENABLE            2

void init_io_ports(void)
{
/* 
* Initialize the quasi-bidirectional port pins.  To use these
* pins as inputs they must be written with a one.
*/

$$ifp$ 80C196KB || 80C196KC || 80C196KD
  _WriteSFR   (ioport1, 0xff);
$$end$
  _WriteSFR   (ioport2, 0xc0);

/*
* IO port pins:
$$ifp$ 80C196KC || 80C196KD
*   p1.3 = $%tioc3.2$pwm1 output$standard i/o$
*   p1.4 = $%tioc3.3$pwm2 output$standard i/o$    
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
*   p1.5 = $%twsr.7$breq#$standard i/o$
*   p1.6 = $%twsr.7$hold#$standard i/o$
*   p1.7 = $%twsr.7$hlda#$standard i/o$
$$end$
*   p2.0 = $%tioc1.5$txd$standard$ output
*   p2.1 = $%tsp_con.3$rxd$standard$ input
*   p2.2 = $%tioc1.1$standard input$EXTINT pin$
*   p2.3 = $%tioc0.7$standard$t2clk$ input
*   p2.4 = $%tioc0.5$t2rst$standard$ input
*   p2.5 = $%tioc1.0$pwm 0$standard$ output
*   p2.6 = $%tioc2.1$t2updn pin$standard i/o$
*/

$$ifp$ 80C196KB || 80C196KC || 80C196KD
  _$%twsr.7$Set$Clr$SFR_bit (wsr, BREQ_HOLD_HOLDA_ENABLE);
$$end$
$$ifp$ 80C196KC || 80C196KD
  _$%tioc3.2$Set$Clr$SFR_bit (ioc3, PWM1_ENABLE);
  _$%tioc3.3$Set$Clr$SFR_bit (ioc3, PWM2_ENABLE);
$$end$
  _$%tioc1.0$Set$Clr$SFR_bit (ioc1, PWM0_ENABLE);
  _$%tioc1.1$Set$Clr$SFR_bit (ioc1, EXTINT_DISABLE);
  _$%tioc1.5$Set$Clr$SFR_bit (ioc1, TXD_ENABLE);

  _$%tioc0.7$Set$Clr$SFR_bit (ioc0, T2CLK_SRC);
  _$%tioc0.5$Set$Clr$SFR_bit (ioc0, T2RST_SRC);

  _$%tioc2.1$Set$Clr$SFR_bit (ioc2, T2UPDN_ENABLE);
  _$%tsp_con.3$Set$Clr$SFR_bit (sp_con, RXD_ENABLE);
}
void main(void)
{
  init_io_ports();
  while(1);
}
##80C194 WDT#
##80C198 WDT#
##80C196KB WDT#
##80C196KC WDT#
##80C196KD WDT#
$$ifp$ 80C198 || 80C194 || 80C196KB
#pragma model(kb)
$$end$
$$ifp$ 80C196KC || 80C196KD
#pragma model(kc)
$$end$
#include <80c196kd.h>

void init_wdt(void)
{
/*
* The watchdog register must be cleared within every 64K
* state times to hold off a watchdog timer reset.  To
* clear the watchdog requires two writes to location 0x0A
* in window 0.  First write 0x1E, then write 0xE1.  The
* first write to 0x0A will enable the watchdog timer.
*/

$$ifp$ 80C198 || 80C194
  wsr = WIN0;
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
  wsr = WIN0 + _HOLDEN;
$$end$
  watchdog = 0x1E;
  watchdog = 0xE1;
}
void main(void)
{
  init_wdt();
  while(1);
}