196a.cod

mcs51,2051,x86系列MCU

cseg
init_extint_src:
  _$%tioc1.1$Set$Clr$SFR_bit ioc1, EXTINT_SRC
  ret

cseg at 2080h
main_extint_src:
  call init_extint_src
  br   $
end
##80C196KC PTS#
##80C196KD PTS#
$include (80c196kd.inc)

; PTS interrupts:
;   timer overflow interrupt          = $%tptssel.0$enabled$disabled$
;   A/D conversion complete interrupt = $%tptssel.1$enabled$disabled$
;   HSI data available interrupt      = $%tptssel.2$enabled$disabled$
;   HSO interrupt                     = $%tptssel.3$enabled$disabled$
;   HSI.0 pin interrupt               = $%tptssel.4$enabled$disabled$
;   software timer interrupt          = $%tptssel.5$enabled$disabled$
;   serial port interrupt             = $%tptssel.6$enabled$disabled$
;   external interrupt                = $%tptssel.7$enabled$disabled$
;   transmit interrupt                = $%tptssel.8$enabled$disabled$
;   receive interrupt                 = $%tptssel.9$enabled$disabled$
;   HSI fifo 4 interrupt              = $%tptssel.10$enabled$disabled$
;   timer 2 capture interrupt         = $%tptssel.11$enabled$disabled$
;   timer 2 overflow interrupt        = $%tptssel.12$enabled$disabled$
;   external interrupt 1              = $%tptssel.13$enabled$disabled$
;   HSI fifo full interrupt           = $%tptssel.14$enabled$disabled$

cseg
init_pts:
  _WriteSFR  int_mask, #0$$int_mask$h
  _WriteSFR  int_mask1, #0$$int_mask1$h
  _WriteSFR  ptssel, #0$$ptssel$h

; $%tpsw.2$Enable$Disable$ global PTS bit

  $%tpsw.2$epts$dpts$
  ret

cseg at 2080h
main_pts_single:
  call init_pts
  br   $
end
##80C196KC PTS_Single#
##80C196KD PTS_Single#
$include (80c196kd.inc)

; This locates the PTS Single mode control block at location
; 50H.  This control block may be located at any quad-word 
; boundary in register space.

rseg at 50h
Single_CntrlBlk_$$PTS_VECTOR$:
  ptscount: dsb 1
  ptscon:      dsb 1
  ptssrc:      dsw 1 
  ptsdst:      dsw 1
  unused$$PTS_VECTOR$:     dsw 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 2040h + (0$$PTS_VECTOR$h * 2)
dcw Single_CntrlBlk_$$PTS_VECTOR$

; The Interrupt vector must contain the address of the
; end-of-pts interrupt service routine.

cseg at 2000h + (@@INT_VECTOR@ * 2)
dcw end_of_pts
   
; The following code is an example of a PTS control block
; initialization sequence.

cseg
init_pts_single_$$PTS_VECTOR$:
  ldb ptscount, #0@@PTSCOUNT@h
  ldb ptscon, #0$$PTSCON$h          
  ld  ptssrc, #0@@PTSSRC@h
  ld  ptsdst, #0@@PTSDST@h
  ret
  
; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

cseg
end_of_pts:
  pusha
    ; User code 
  popa
  ret
   
cseg at 2080h
  call init_pts_single_$$PTS_VECTOR$
  br   $
end

##80C196KC PTS_Block#
##80C196KD PTS_Block#
$include (80c196kd.inc)

; This locates the PTS Block mode control block at location
; 50H.  This control block may be located at any quad-word 
; boundary in register space.

rseg at 50h
Block_CntrlBlk_$$PTS_VECTOR$:
  ptscount: dsb 1
  ptscon:   dsb 1
  ptssrc:      dsw 1
  ptsdst:         dsw 1
  ptsblock:    dsb 1
  unused$$PTS_VECTOR$:     dsb 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 2040h + (0$$PTS_VECTOR$h * 2)
  dcw Block_CntrlBlk_$$PTS_VECTOR$

; The Interrupt vector must contain the address of the
; end-of-pts interrupt service routine.

cseg at 2000h + (@@INT_VECTOR@ * 2)
  dcw end_of_pts

; The following code is an example of a PTS control block
; initialization sequence.

cseg
init_pts_block_$$PTS_VECTOR$:
  ldb ptscount, #0@@PTSCOUNT@h
  ldb ptscon, #0$$PTSCON$h
  ld  ptssrc, #0@@PTSSRC@h
  ld  ptsdst, #0@@PTSDST@h
  ldb ptsblock, #0@@PTSBLOCK@h
  ret
  
; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

cseg
end_of_pts:
  pusha
    ; User code
  popa
  ret
   
cseg at 2080h
main_pts_block:
  call init_pts_block_$$PTS_VECTOR$
  br   $
end

##80C196KC PTS_AD#
##80C196KD PTS_AD#
$include (80c196kd.inc)

; This locates the PTS AD Scan mode control block at location
; 50H.  This control block may be located at any quad-word 
; boundary in register space. 

rseg at 50h
Ad_CntrlBlk_$$PTS_VECTOR$:
  ptscount:    dsb   1
  ptscon:   dsb   1
  pts_src_dst: dsw   1
  ptsreg:   dsw   1
  unused$$PTS_VECTOR$:     dsw   1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 2040h + (0$$PTS_VECTOR$h * 2)
  dcw Ad_CntrlBlk_$$PTS_VECTOR$

; The Interrupt vector must contain the address of the
; end-of-pts interrupt service routine.

cseg at 2000h + (@@INT_VECTOR@ * 2)
  dcw end_of_pts

; This allows the AD table of commands and results to be
; relocatable in the data segment.  This table can also
; reside in register space.

dseg
@@PTS_AD_TBL@:
  ad_cmd1:     DSW 1
  ad_rslt1:    DSW 1
  ad_cmd2:     DSW 1
  ad_rslt2:    DSW 1
  ad_cmd3:     DSW 1
  ad_rslt3:    DSW 1
  ad_cmd4:     DSW 1
  ad_rslt4:    DSW 1
  ad_cmd5:     DSW 1
  ad_rslt5:    DSW 1
  ad_cmd6:     DSW 1
  ad_rslt6:    DSW 1
  ad_cmd7:     DSW 1
  ad_rslt7:    DSW 1
  dum_cmd:     DSW 1

; The following code is an example of a PTS control block
; initialization sequence.

cseg
init_pts_ad_$$PTS_VECTOR$:
  di           ;disable all interrupts
  dpts            ;disable pts interrupts
  ldb ptscount, #0@@PTSCOUNT@
  ldb ptscon, #1100$$PTSCON.3$010B
  ld  pts_src_dst, @@PTS_AD_TBL@
  ld  ptsreg, #02h         ;addrs of ad_command

; The following code will load a table of AD commands starting
; at the location specified by @@PTS_AD_TBL@. The commands
; will start AD conversions on AD Channels 0 - 7.

  ldb tmpreg, #09h         ;chn1, start immed
  stb tmpreg, ad_cmd1[zero_reg]
  ldb tmpreg, #0ah         ;chn2, start immed
  stb tmpreg, ad_cmd2[zero_reg]
  ldb tmpreg, #0bh         ;chn3, start immed
  stb tmpreg, ad_cmd3[zero_reg]
  ldb tmpreg, #0ch         ;chn4, start immed
  stb tmpreg, ad_cmd4[zero_reg]
  ldb tmpreg, #0dh         ;chn5, start immed
  stb tmpreg, ad_cmd5[zero_reg]
  ldb tmpreg, #0eh         ;chn6, start immed
  stb tmpreg, ad_cmd6[zero_reg]
  ldb tmpreg, #0fh         ;chn7, start immed
  stb tmpreg, ad_cmd7[zero_reg]
  ldb tmpreg, #00h         ;stop doing A/D scans
                  ;after chn7
  stb tmpreg, dum_cmd[zero_reg]

; To enable PTS the A/D interrupt INT_MASK.1 and PTSSEL.1
; must be set. Checking the 'Enable the PTS Interrupt' box 
; will set these bits clearing the box will clear these bits.
  
  _$%tint_mask.1$Clr$Set$SFR_bit int_mask, 1
  _$%tptssel.1$Clr$Set$SFR_bit ptssel, 1
  _WriteSFR ad_command, #8h   ;chn0, start immed 
  ei           ;enable normal AD interrupt 
  epts            ;enable PTS
  ret
   
; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

cseg
end_of_pts:
  pusha

    ; User code - called when scan is finished
    ; user needs to reinitialize the A/D PTS control block
    ; if desired.

  popa
  ret

cseg at 2080h
main_pts_ad:
  call init_pts_ad_$$PTS_VECTOR$
  br   $
end

##80C196KC PTS_HSO#
##80C196KD PTS_HSO#
$include (80c196kd.inc)

; This locates the PTS HSO mode control block at location
; 50H.  This control block may be located at any quad-word 
; boundary in register space. 

rseg at 50h
HSO_CntrlBlk_$$PTS_VECTOR$:
  ptscount:    dsb 1
  ptscon:   dsb 1
  ptssrc:      dsw 1
  unused$$PTS_VECTOR$a:       dsw 1
  ptsblock: dsb 1
  unused$$PTS_VECTOR$b:       dsb 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 2040h + (0$$PTS_VECTOR$h * 2)
  dcw HSO_CntrlBlk_$$PTS_VECTOR$

; The Interrupt vector must contain the address of the
; end-of-pts interrupt service routine.

cseg at 2000h + (@@INT_VECTOR@ * 2)
  dcw end_of_pts

; This allows the HSO table of commands to be relocatable
; in the data segment.  This table can also reside in
; register space.

dseg
@@PTS_SRC_TBL@:
  hso_cmd0: dsw 1
  hso_tm0:  dsw 1
  hso_cmd1: dsw 1
  hso_tm1:  dsw 1
  hso_cmd2: dsw 1
  hso_tm2:  dsw 1
  hso_cmd3: dsw 1
  hso_tm3:  dsw 1
  hso_cmd4: dsw 1
  hso_tm4:  dsw 1
  hso_cmd5: dsw 1
  hso_tm5:  dsw 1
  hso_cmd6: dsw 1
  hso_tm6:  dsw 1
  hso_cmd7: dsw 1
  hso_tm7:  dsw 1

; The following code is an example of a PTS control block
; initialization sequence.

cseg
init_pts_hso_$$PTS_VECTOR$:
  ldb ptscount, #0@@PTSCOUNT@h
  ldb ptscon, #0$$PTSCON$h 
  ld  ptssrc, @@PTS_SRC_TBL@
  ldb ptsblock, #0@@PTSBLOCK@h
  ret
  
; The following code is an example of an HSO table of
; commands. The table fills the CAM and the holding
; register.  The location of the table is specified by
; @@PTS_SRC_TBL@
;
; ldb tmpreg, <enter hso command 0>
; stb tmpreg, hso_cmd0[zero_reg]
; ld  tmpreg, <enter time 0>
; st  tmpreg, hso_tm0[zero_reg]
; ldb tmpreg, <enter hso command 1>
; stb tmpreg, hso_cmd1[zero_reg]
; ld  tmpreg, <enter time 1>
; st  tmpreg, hso_tm1[zero_reg]
; ldb tmpreg, <enter hso command 2> 
; stb tmpreg, hso_cmd2[zero_reg]
; ld  tmpreg, <enter time 2>
; st  tmpreg, hso_tm2[zero_reg]
; ldb tmpreg, <enter hso command 3>
; stb tmpreg, hso_cmd3[zero_reg]
; ld  tmpreg, <enter time 3>
; st  tmpreg, hso_tm3[zero_reg]
; ldb tmpreg, <enter hso command 4>
; stb tmpreg, hso_cmd4[zero_reg]
; ld  tmpreg, <enter time 4>
; st  tmpreg, hso_tm4[zero_reg]
; ldb tmpreg, <enter hso command 5>
; stb tmpreg, hso_cmd5[zero_reg]
; ld  tmpreg, <enter time 5>
; st  tmpreg, hso_tm5[zero_reg]
; ldb tmpreg, <enter hso command 6>
; stb tmpreg, hso_cmd6[zero_reg]
; ld  tmpreg, <enter time 6> 
; st  tmpreg, hso_tm6[zero_reg]
; ldb tmpreg, <enter hso command 7>
; stb tmpreg, hso_cmd7[zero_reg]
; ld  tmpreg, <enter time 7>
; st  tmpreg, hso_tm7[zero_reg]

; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

cseg
end_of_pts:
  pusha

    ;User code

  popa
  ret

cseg at 2080h
  call init_pts_hso_$$PTS_VECTOR$
  br   $
end

##80C196KC PTS_HSI#
##80C196KD PTS_HSI#
$include (80c196kd.inc)

; This locates the PTS HSI mode control block at location
; 50H.  This control block may be located at any quad-word 
; boundary in register space. 

rseg at 50h
HSI_CntrlBlk_$$PTS_VECTOR$:
  ptscount:    dsb 1
  ptscon:      dsb 1
  ptsdst:      dsw 1
  unused$$PTS_VECTOR$a:    dsw 1
  ptsblock: dsb 1
  unused$$PTS_VECTOR$b:    dsb 1

; The PTS vector must contain the address of the PTS control
; block.

cseg at 2040h + (0$$PTS_VECTOR$h * 2)
  dcw HSI_CntrlBlk_$$PTS_VECTOR$

; The Interrupt vector must contain the address of the
; end-of-pts interrupt service routine.

cseg at 2000h + (@@INT_VECTOR@ * 2)
  dcw end_of_pts

; This allows the HSI FIFO table to be relocatable in the data
; segment.  This table can also reside in register space.

dseg
  @@PTS_DST_TBL@: dsw 16

; The following code is an example of a PTS control block
; initialization sequence.

cseg
init_pts_hsi_$$PTS_VECTOR$:
  ldb ptscount, #0@@PTSCOUNT@h
  ldb ptscon, #0$$PTSCON$h
  ld  ptsdst, @@PTS_DST_TBL@ 
  ldb ptsblock, #0@@PTSBLOCK@h
  ret
  
; When the PTS cycle is finished it will generate an end-of-pts
; interrupt.

cseg
end_of_pts:
  pusha

    ;User code

  popa
ret

cseg at 2080h
  call init_pts_hsi_$$PTS_VECTOR$
  br   $
end

##80C194 IO#
##80C198 IO#
##80C196KB IO#
##80C196KC IO#
##80C196KD IO#
$include (80c196kd.inc)
$$ifp$ 80C196KC || 80C196KD
 PWM1_ENABLE              equ   4h
 PWM2_ENABLE              equ   8h
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
 BREQ_HOLD_HOLDA_ENABLE   equ   7
$$end$
 TXD_ENABLE               equ   6h
 RXD_ENABLE               equ   3
 EXTINT_DISABLE           equ   2h  
 T2CLK_SRC                equ   80h
 T2RST_SRC                equ   20h
 PWM0_ENABLE              equ   1h
 T2UPDN_ENABLE            equ   1
 
; Initialize the quasi-bidirectional port pins.  To use these
; pins as inputs they must be written with a one.

cseg
init_io_ports:
$$ifp$ 80C196KB || 80C196KC || 80C196KD
  _WriteSFR  ioport1, #0ffh
$$end$
  _WriteSFR  ioport2, #0c0h

; IO port pins:
$$ifp$ 80C196KC || 80C196KD
;   p1.3 = $%tioc3.2$pwm1 output$standard i/o$
;   p1.4 = $%tioc3.3$pwm2 output$standard i/o$    
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
;   p1.5 = $%twsr.7$breq#$standard i/o$
;   p1.6 = $%twsr.7$hold#$standard i/o$
;   p1.7 = $%twsr.7$hlda#$standard i/o$
$$end$
;   p2.0 = $%tioc1.5$txd$standard$ output
;   p2.1 = $%tsp_con.3$rxd$standard$ input
;   p2.2 = $%tioc1.1$standard input$EXTINT pin$
;   p2.3 = $%tioc0.7$t2clk$standard$ input
;   p2.4 = $%tioc0.5$standard$t2rst$ input
;   p2.5 = $%tioc1.0$pwm 0$standard$ output
;   p2.6 = $%tioc2.1$t2updn pin$standard i/o$

$$ifp$ 80C196KB || 80C196KC || 80C196KD
  _$%twsr.7$Set$Clr$SFR_bit wsr, BREQ_HOLD_HOLDA_ENABLE
$$end$
$$ifp$ 80C196KC || 80C196KD
  _$%tioc3.2$Set$Clr$SFR_bit ioc3, PWM1_ENABLE
  _$%tioc3.3$Set$Clr$SFR_bit ioc3, PWM2_ENABLE
$$end$
  _$%tioc1.0$Set$Clr$SFR_bit ioc1, PWM0_ENABLE
  _$%tioc1.1$Set$Clr$SFR_bit ioc1, EXTINT_DISABLE
  _$%tioc1.5$Set$Clr$SFR_bit ioc1, TXD_ENABLE

  _$%tioc0.7$Set$Clr$SFR_bit ioc0, T2CLK_SRC
  _$%tioc0.5$Set$Clr$SFR_bit ioc0, T2RST_SRC

  _$%tioc2.1$Set$Clr$SFR_bit ioc2, T2UPDN_ENABLE
  _$%tsp_con.3$Set$Clr$SFR_bit sp_con, RXD_ENABLE 
  ret

cseg at 2080h
main_io_ports:
  call init_io_ports
  br   $
end
##80C194 WDT#
##80C198 WDT#
##80C196KB WDT#
##80C196KC WDT#
##80C196KD WDT#
$include (80c196kd.inc)

; The watchdog register must be cleared within every 64K
; state times to hold off a watchdog timer reset.  To
; clear the watchdog requires two writes to location 0AH
; in window 0.  First write 1EH, then write E1H.  The
; first write to 0AH will enable the watchdog timer.

cseg
init_wdt:
$$ifp$ 80C198 || 80C194
  ldb wsr, #WIN0
$$end$
$$ifp$ 80C196KB || 80C196KC || 80C196KD
  ldb wsr, #WIN0 + _HOLDEN
$$end$
  ldb watchdog, #01Eh
  ldb watchdog, #0E1h
  ret

cseg at 2080h
main_wdt:
  call init_wdt
  br   $
end