📄 196a.cod
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/*
* Copyright (c) 1995, Intel Corporation
*
* $Workfile: 196a.cod $
* $Revision: 1.1 $
* $Modtime: Mar 22 1995 16:58:04 $
*
* Purpose:
*
*
*
*
*
* Compiler:
*
* Ext Packages:
*
*
*
*/
196KD/KC/KB 198/184
##80C196K? WRITE#
##80C19? WRITE#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
$$IFSTR$ REG_MNEM "CCR"
CSEG AT 2018H
DCB #$%aREG_VALUE$
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
LDB wsr, #$%aWSR_WRITE$
LDB @@REG_MNEM@, #$%aREG_VALUE & 0xff$
LDB @@REG_MNEM@, #$%aREG_VALUE > 8$
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
LDB wsr, #$%aWSR_WRITE$
LDB @@REG_MNEM@, #01Eh
LDB @@REG_MNEM@, #0E1h
$$END$
$$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
_WriteSFR @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_WRITE$
$$END$
LD@@REG_SIZE@ @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$END$
##80C196K? READ#
##80C19? READ#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
$$IFSTR$ REG_MNEM "CCR"
CSEG AT 2018H
DCB #$%aREG_VALUE$
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
_ReadSFR UserVar, @@REG_MNEM@
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
ST@@REG_SIZE@ @@REG_MNEM@, UserVar
$$END$
$$END$
##80C196K? OR#
##80C19? OR#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
$$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
_OrSFR @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
$$IF$ REG_WSRSAME || REG_WSRALL
OR@@REG_SIZE@ @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$IFN$ REG_WSRSAME &! REG_WSRALL
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
OR@@REG_SIZE@ UserVar, #$%aREG_VALUE$
LDB wsr, #$%aREG_WSRWRITE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
$$END$
##80C196K? AND#
##80C19? AND#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
$$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
_AndSFR @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
$$IF$ REG_WSRSAME || REG_WSRALL
AND@@REG_SIZE@ @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$IFN$ REG_WSRSAME &! REG_WSRALL
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
AND@@REG_SIZE@ UserVar, #$%aREG_VALUE$
LDB wsr, #$%aREG_WSRWRITE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
$$END$
##80C196K? XOR#
##80C19? XOR#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG" |STR "IOPORT0"
$$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "IOPORT0"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$END$
$$ELSE$
$$IF$ REG_USEMACRO
_XorSFR @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
$$IF$ REG_WSRSAME || REG_WSRALL
XOR@@REG_SIZE@ @@REG_MNEM@, #$%aREG_VALUE$
$$END$
$$IFN$ REG_WSRSAME &! REG_WSRALL
LD@@REG_SIZE@ UserVar, @@REG_MNEM@
XOR@@REG_SIZE@ UserVar, #$%aREG_VALUE$
LDB wsr, #$%aREG_WSRWRITE$
ST@@REG_SIZE@ UserVar, @@REG_MNEM@
$$END$
$$END$
$$END$
##80C196K? TESTZ#
##80C19? TESTZ#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
$$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
AND@@REG_SIZE@ zero_reg, @@REG_MNEM@, #$%aREG_VALUE$
JE <Dest. Label>
$$END$
##80C196K? TESTNZ#
##80C19? TESTNZ#
$$IFSTR$ REG_MNEM "CCR" |STR "BAUD_RATE" |STR "WATCHDOG"
$$IFSTR$ REG_MNEM "CCR"
Unsupported Operation:
@@REG_MNEM@ register is a read-only register.
$$END$
$$IFSTR$ REG_MNEM "BAUD_RATE"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$IFSTR$ REG_MNEM "WATCHDOG"
Unsupported Operation:
@@REG_MNEM@ register is a write-only register.
$$END$
$$END$
$$ELSE$
$$IFN$ REG_WSRALL
LDB wsr, #$%aWSR_READ$
$$END$
AND@@REG_SIZE@ zero_reg, @@REG_MNEM@, #$%aREG_VALUE$
JNE <Dest. Label>
$$END$
##80C198 AD#
##80C196KB AD#
##80C196KC AD#
##80C196KD AD#
$include (80c196kd.inc)
ATOD_BUSY set (ad_result and 008)
GO_NOW set 008h
GO_EPA set 000h
TEN_BIT_MODE set 000h
EIGHT_BIT_MODE set 010h
$$ifp$ 80C198 || 80C194 || 80C196KB
AD_SPEED equ 4
$$end$
$$ifp$ 80C196KC || 80C196KD
AD_COMPAT equ 3
$$ifn$ IOC2.3
AD_SPEED equ 4
$$end$
$$end$
AD_INT equ 1
; A/D conversion configuration:
$$ifp$ 80C198 || 80C194 || 80C196KB
; speed = $%tioc2.4$fast$normal$
$$end$
; interrupt = $%tINT_MASK.1$enabled$disabled$
$$ifp$ 80C198
; channel = $%4AD_COMMAND.0-2$4$5$6$7$
$$end$
$$ifnp$ 80C198
; channel = $$AD_COMMAND.0-2$
$$end$
; start time = $%TAD_COMMAND.3$started immediately$triggered by the HSO$
$$ifp$ 80C198 || 80C194 || 80C196KB
; mode = $%tAD_COMMAND.4$8-bit$10-bit$
$$end$
$$ifp$ 80C196KC || 80C196KD
; mode = $%tioc2.3$configurable$compat$
$$ifn$ IOC2.3
; speed = $%tioc2.4$fast$normal$
$$end$
$$if$ IOC2.3
; sample time = @@SAMP_TM@ microseconds
; conversion time = @@CONV_TM@ microseconds
$$end$
$$end$
cseg
init_atod_converter:
$$ifp$ 80C196KC || 80C196KD
_$%tIOC2.3$Set$Clr$SFR_bit ioc2, AD_COMPAT
$$ifn$ IOC2.3
_$%tIOC2.4$Set$Clr$SFR_bit ioc2, AD_SPEED
$$end$
$$if$ IOC2.3
_WriteSFR ad_time, #0$$AD_TIME$h
$$end$
$$end$
$$ifp$ 80C198 || 80C194 || 80C196KB
_$%tIOC2.4$Set$Clr$SFR_bit ioc2, AD_SPEED
$$end$
_$%tINT_MASK.1$Set$Clr$SFR_bit int_mask, AD_INT
ret
$$ifn$ INT_MASK.1
; convert_atod:
; Performs $%tAD_COMMAND.4$an 8$a 10$-bit A/D conversion and returns
; the result. This routine waits until the A/D busy bit
; is cleared before and after the conversion. If the
; A/D interrupt is used then the results of this
; routine may be erronous.
cseg
convert_atod:
clrb wsr
jbs ad_result_lo, 3, $
ldb tmpreg, 2[sp]
ldb ad_command, #$%tAD_COMMAND.3$GO_NOW$GO_EPA$ + $%tAD_COMMAND.4$EIGHT$TEN$_BIT_MODE
$$if$ AD_COMMAND.3
ldb zero_reg, zero_reg ;4 state delay needed
ldb zero_reg, zero_reg ;4 state delay needed
jbs ad_result_lo, 3, $
$$ifn$ AD_COMMAND.4
ld tmpreg, ad_result
shr tmpreg, #6
$$end$
$$if$ AD_COMMAND.4
ldbze tmpreg, ad_result_hi
$$end$
$$end$
ret
$$end$
; main_atod:
; Program the A/D to perform a$%tAD_COMMAND.4$n 8-bit$ 10-bit$ conversion.
; on A/D channel $$AD_COMMAND.0-2$.
;
; The A/D conversion will be $%TAD_COMMAND.3$started immediately$triggered by the EPA$
cseg at 02080h
main_atod:
ld sp, #STACK
call init_atod_converter
$$if$ INT_MASK.1
ei ;globally enable interrupts
clrb wsr;
ldb ad_command, #0$$AD_COMMAND$h
br $ ;wait for A/D interrupt
$$end$
$$ifn$ INT_MASK.1 && AD_COMMAND.3
push #0$$AD_COMMAND.0-2$H
call convert_atod
add sp, #2
; tmpreg now contains the result of the conversion which
; can be now be acted upon.
br $
$$end$
$$ifn$ INT_MASK.1 &! AD_COMMAND.3
push #0$$AD_COMMAND.0-2$H
call convert_atod
add sp, #2
br $ ;wait for epa to trigger A/D
;the result should be serviced
;with an interrupt routine.
$$end$
$$if$ INT_MASK.1
cseg at 2002h
atod_vector: dcw atod_interrupt
; The atod_interrupt routine will be vectored to if interrupts
; are enabled and an A/D conversion has completed.
cseg
atod_interrupt:
pusha
push tmpreg
clrb wsr
$$ifn$ AD_COMMAND.5 &! AD_COMMAND.4
ld tmpreg, ad_result
shr tmpreg, #6
; tmpreg can now be stored or acted upon by the user's code.
$$end$
$$ifn$ AD_COMMAND.5 && AD_COMMAND.4
ldb tmpreg, ad_result_hi
; tmpreg can now be stored or acted upon by the user's code.
$$end$
pop tmpreg
popa
ret
$$end$
end
##80C194 PWM#
##80C198 PWM#
##80C196KB PWM#
##80C196KC PWM0#
##80C196KD PWM0#
##80C196KC PWM1#
##80C196KD PWM1#
##80C196KC PWM2#
##80C196KD PWM2#
$include (80c196kd.inc)
$$if$ (PWM_NUMBER == 0)
PWM$$PWM_NUMBER$_ENABLE equ 0
$$end$
$$if$ (PWM_NUMBER == 1)
PWM$$PWM_NUMBER$_ENABLE equ 2
$$end$
$$if$ (PWM_NUMBER == 2)
PWM$$PWM_NUMBER$_ENABLE equ 3
$$end$
PWM_PRESCALE equ 2
; PWM$$PWM_NUMBER$ configuration:
; prescaler mode = divide by $%tIOC2.2$2$1$
; PWM output = $%tIOC1.0$enabled$disabled$
; PWM duty cycle = @@PWM_DUTY_CYCLE@ %
;
; pwm$$PWM_NUMBER$_control = 256 * (Duty Cycle) / 100
cseg
init_pwm$$PWM_NUMBER$:
_$%tIOC2.2$Set$Clr$SFR_bit ioc2, PWM_PRESCALE
$$if$ (PWM_NUMBER == 0)
_WriteSFR pwm$$PWM_NUMBER$_control, #0$$PWM0_CONTROL$h
_$%tIOC1.0$Set$Clr$SFR_bit ioc1, PWM$$PWM_NUMBER$_ENABLE
$$end$
$$if$ (PWM_NUMBER == 1)
_WriteSFR pwm$$PWM_NUMBER$_control, #0$$PWM1_CONTROL$h
_$%tIOC3.2$Set$Clr$SFR_bit ioc3, PWM$$PWM_NUMBER$_ENABLE
$$end$
$$if$ (PWM_NUMBER == 2)
_WriteSFR pwm$$PWM_NUMBER$_control, #0$$PWM2_CONTROL$h
_$%tIOC3.3$Set$Clr$SFR_bit ioc3, PWM$$PWM_NUMBER$_ENABLE
$$end$
ret
cseg at 2080h
main_pwm$$PWM_NUMBER$:
call init_pwm$$PWM_NUMBER$
br $
end
##80C194 Serial#
##80C198 Serial#
##80C196KB Serial#
##80C196KC Serial#
##80C196KD Serial#
$include (80c196kd.inc)
SP_MODE0 set 000h
SP_MODE1 set 001h
SP_MODE2 set 002h
SP_MODE3 set 003h
REC_ENABLE set 008h
REC_DISABLE set 000h
EVEN_PARITY set 008h
ODD_PARITY set 028h
NO_PARITY set 000h
SET_BIT_8 set 004h
SP_INTERNAL_CLK set 08000h
SP_EXTERNAL_CLK set 00000h
TXD_INTERRUPT set 001h
RXD_INTERRUPT set 002h
SERIAL_INT set 040h
TI_BIT set 005h
RI_BIT set 006h
FE_BIT set 004h
OE_BIT set 002h
RPE_BIT set 007h
RB8_BIT set 007h
TXE_BIT set 003h
_SetBitReg macro regnum,bitnum
orb regnum,#( 1 SHL bitnum )
endm
_ClrBitReg macro regnum,bitnum
andb regnum,#not( 1 SHL bitnum )
endm
rseg
sp_status_image: dsb 1
$$ifn$ INT_MASK1.1 |! INT_MASK1.0 |! INT_MASK.6
$$ifn$ INT_MASK1.0 &! INT_MASK.6 && IOC1.5
cseg
putchar:
_ReadSFR tmpreg, sp_stat
orb sp_status_image, tmpreg
jbc sp_status_image, TXE_BIT, putchar
clr_bit sp_status_image, TXE_BIT
$$if$ SP_CON.4
; If bit 8 needs to be set, then the following line needs to
; be inserted:
; _OrSFR_bit sp_con, SET_BIT_8
$$end$
_WriteSFR sbuf, 2[sp]
ret
$$end$
$$ifn$ INT_MASK1.1 &! INT_MASK.6 && SP_CON.3
cseg
getchar:
_ReadSFR tmpreg, sp_stat
orb sp_status_image, tmpreg
jbc sp_status_image, RI_BIT, getchar
jbc sp_status_image, FE_BIT, no_frame_error
; User code for framing error
andb sp_status_image, #FE_BIT
no_frame_error:
jbc sp_status_image, OE_BIT, no_overrun_error
; User code for overrun error
_ClrBitReg sp_status_image, OE_BIT
no_overrun_error:
$$if$ SP_CON.2
jbc sp_status_image, RPE_BIT, no_parity_error
; User code for Parity error
_ClrBitReg sp_status_image, RPE_BIT
no_parity_error:
$$end$
$$if$ SP_CON.4
jbc sp_status_image, RB8_BIT, no_8th_bit
; User code for Receiving BIT 8
_ClrBitReg sp_status_image, RB8_BIT
no_8th_bit:
$$end$
_ReadSFR tmpreg, sbuf
ret
$$end$
$$end$
$$if$ INT_MASK1.0-1 || INT_MASK.6
$$if$ INT_MASK1.1
cseg at 2032h
rx_vector: dcw receive
$$end$
$$if$ INT_MASK1.0
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