196npc.cod

mcs51,2051,x86系列MCU

#define   DEFERRED_MODE_ENAB 0x20
#define   DEFERRED_MODE_DISAB 0x00
$$end$

static const unsigned int CCB[] =
          { 0x2000 |
            CCR0_RESERVED |
            $%4CCR0.4-5$ZERO$ONE$TWO$THREE$_WAIT_STATES |
            POW_DN_$%TCCR0.0$ENABLE$DISABLE$ |
            $%TCCR0.2$WR_BHE$WRL_WRH$ |
            $%TCCR0.3$DEMUXED$MUXED$_MODE |
            BUS_WIDTH_$%TCCR0.1$16$8$,

            0x2000 | 
            CCR0_RESERVED |
$$ifp$80c196np
            $%TCCR1.2$REMAP_ROM$NO_ROM_REMAP$ |
$$end$
$$ifp$80c196nu
            $%TCCR1.5$DEFERRED_MODE_ENAB$DEFERRED_MODE_DISAB$ |
$$end$
            $%TCCR1.1$MODE64$MODE1MEG$ |
            CCR1_RESERVED};

#pragma locate (CCB=0x00FF2018)

$$if$  WSR.7
#define   HOLD_CONTROL   0x80
void init_hold_holda()
{
 /*  init the hold, holda, and breq pins to special function  */

 p2_reg |= 0x68;       /*  init hold#  */
 p2_dir &= 0xB7;       /*  make hlda, breq outputs  */
 setbit(p2_dir, 5)     /*  make hold  input  */
 p2_mode |= 0x68       /*  make special function */
 wsr |= HOLD_CONTROL;
} 
$$end$

$$ifp$80c196nu
void init_accumulator()
{
   acc_stat=0x0$%TACC_STAT.6$ | SAT_MODE_ENAB$$$%TACC_STAT.7$ | FRACT_MODE_ENAB$$;
}

$$ifn$ WSR.7
void main(void)
{
$$end$
$$end$
$$if$ WSR.7
void main(void)
{
   init_hold_holda();
$$end$
$$ifp$80c196nu
   init_accumulator();
   
/*   Users code   */

$$if$ WSR.7
/*  To change wsr use:

 wsr = HOLD_CONTROL | WINDOW_VALUE;
*/
$$end$ 
 while(1);
}
$$end$
$$ifp$80c196np
$$if$ WSR.7
 
/*   Users code   */

/*  To change wsr use:
 wsr = HOLD_CONTROL | WINDOW_VALUE;
*/ 
 while(1);
} 
$$end$
$$end$
##80C196NP ICU#
##80C196NU ICU#
$$ifp$80c196np
#pragma model(NP)
#include <80c196np.h>
$$end$
$$ifp$80c196nu
#pragma model(NU)
#include <80c196nu.h>
$$end$

void init_interrupts(void)
{
 int_mask = 0x$$INT_MASK$;
 int_mask1 = 0x$$INT_MASK1$;
}
$$if$ INT_MASK.0

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(timer1_ovr_template = 0)
void timer1_ovr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK.1

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(timer2_ovr_template = 1)
void timer2_ovr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK.2

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(reserved2 = 2)
void reserved2(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK.3

#pragma interrupt(extint0_isr_template = 3)
void extint0_isr_template(void)
{
 ******** user code *******
}
$$end$
$$if$ INT_MASK.4

#pragma interrupt(extint1_isr_template = 4)
void extint1_isr_template(void)
{
 ******** user code *******
}
$$end$
$$if$ INT_MASK.5

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(TXD_isr_template = 5)
void TXD_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK.6

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(RXD_isr_template = 6)
void RXD_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK.7

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA0_isr_template = 7)
void EPA0_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.0

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA1_isr_template = 24)
void EAP1_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.1

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA2_isr_template = 25)
void EPA2_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.2

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA3_isr_template = 26)
void EPA3_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.3

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA0_1_OVR_isr_template = 27)
void EPA0_1_OVR_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.4

/*   Enabling of the this Interrupt should be generated 
     using the peripheral editor.  The following can be used for 
     template. 
#pragma interrupt(EPA2_3_OVR_isr_template = 28)
void EPA2_3_OVR_isr_template(void)
{
 ******** user code *******
}
*/
$$end$
$$if$ INT_MASK1.5
#pragma interrupt(EXTINT2_isr_template = 29)
void EXTINT2_isr_template(void)
{
 ******** user code *******
}
$$end$
$$if$ INT_MASK1.6
#pragma interrupt(EXTINT3_isr_template = 30)
void EXTINT3_isr_template(void)
{
 ******** user code *******
}
$$end$

/*   The following can be used for  template to handle a TRAP 
     interrupt.

#pragma interrupt(TRAP_isr_template = 8)
void TRAP_isr_template(void)
{
 ******** user code *******
}
*/

/*   The following can be used for  template to handle a un-
     implimented opcode.

#pragma interrupt(UN_IMP_OPCODE_isr_template = 9)
void UN_IMP_OPCODE_isr_template(void)
{
 ******** user code *******
}
*/

/*   The following can be used for  template to handle a Non-
     Maskable-Interrupt.

#pragma interrupt(NMI_isr_template = 31)
void NMI_isr_template(void)
{
 ******** user code *******
}
*/

void main(void)
{
 init_interrupts();
$$if$ PSW.1
 enable();
$$end$ 
 while(1);     /*  wait for interrupts to occur   */
}
##80C196NP PTS#
##80C196NU PTS#
$$ifp$80c196np
#pragma model(NP)
#include <80c196np.h>
$$end$
$$ifp$80c196nu
#pragma model(NU)
#include <80c196nu.h>
$$end$
#define   PTS_TIMER1          0x0001
#define   PTS_TIMER2          0x0002
#define   PTS_EXTINT0         0x0008
#define   PTS_EXTINT1         0x0010
#define   PTS_TI              0x0020
#define   PTS_RI              0x0040
#define   PTS_EPA0            0x0080
#define   PTS_EPA1            0x0100
#define   PTS_EPA2            0x0200
#define   PTS_EPA3            0x0400
#define   PTS_EPA0_1_OVR      0x0800
#define   PTS_EPA2_3_OVR      0x1000
#define   PTS_EXTINT2         0x2000
#define   PTS_EXTINT3         0x4000
#define   PTS_DONE            0x00

void init_global_pts()
{
 ptssel =
$$if$ PTSSEL.0
               PTS_TIMER1 |
$$end$
$$if$ PTSSEL.1
               PTS_TIMER2 |
$$end$
$$if$ PTSSEL.3
               PTS_EXTINT0 |
$$end$
$$if$ PTSSEL.4
               PTS_EXTINT1 |
$$end$
$$if$ PTSSEL.5
               PTS_TI |
$$end$
$$if$ PTSSEL.6
               PTS_RI |
$$end$
$$if$ PTSSEL.7
               PTS_EPA0 |
$$end$
$$if$ PTSSEL.8
               PTS_EPA1 |
$$end$
$$if$ PTSSEL.9
               PTS_EPA2 |
$$end$
$$if$ PTSSEL.10
               PTS_EPA3 |
$$end$
$$if$ PTSSEL.11
               PTS_EPA0_1_OVR |
$$end$
$$if$ PTSSEL.12
               PTS_EPA2_3_OVR |
$$end$
$$if$ PTSSEL.13
               PTS_EXTINT2 |
$$end$
$$if$ PTSSEL.14
               PTS_EXTINT3 |
$$end$
               PTS_DONE;    /*  Needed to end conditional code  */
$$if$ PSW.2
 enable_pts();
$$end$
}
##80C196NP PTS_Single#
##80C196NU PTS_Single#
$$ifp$80c196np
#pragma model(NP)
#include <80c196np.h>
$$end$
$$ifp$80c196nu
#pragma model(NU)
#include <80c196nu.h>
$$end$

#define   PTS_BLOCK_BASE      0x0$%XPTS_VECTOR * 8 + 0x380$
/*
   Initialization Code for Single Transfer for
   PTS vector 0x$%XPTS_VECTOR$
*/

/*
   Create typedef template for the single transfer control
   block.
*/
typedef struct SingleTran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc;
                             void  *ptsdst;
                             int   :16; /* unused */
                             } SingleTran_ptscb;

/*
   This locates the PTS Single mode control block in register
   ram.  This control block may be located at any quad-word
   boundary in register space.
*/
SingleTran_ptscb Single_CB_$%dPTS_VECTOR$;
#pragma locate(Single_CB_$%dPTS_VECTOR$=PTS_BLOCK_BASE)

/*
   The PTS vector must contain the address of the PTS control
   block.
*/
#pragma pts(Single_CB_$%dPTS_VECTOR$=0x$%XPTS_VECTOR$)

/*
   The following code is an example of a PTS control block
   initialization sequence.
*/
void Init_SingleTrans_PTS_$%dPTS_VECTOR$(void)
{
    Single_CB_$%dPTS_VECTOR$.ptscount = 0x@@PTSCOUNT@;
    Single_CB_$%dPTS_VECTOR$.ptssrc   = (void *)0x@@PTSSRC@;
    Single_CB_$%dPTS_VECTOR$.ptsdst   = (void *)0x@@PTSDST@;
    Single_CB_$%dPTS_VECTOR$.ptscon   = 0x$$PTSCON$;
$$if$ PTSSEL_ENABLE
    setbit(ptssel, 0x$%XPTS_VECTOR$);
$$end$
$$if$ (PTS_VECTOR > 7)
    setbit(int_mask1, 0x$%XPTS_VECTOR$ - 8);
$$end$
$$if$ (PTS_VECTOR < 8)
    setbit(int_mask, 0x$%XPTS_VECTOR$);
$$end$
$$if$  PSW.2
    enable_pts();
$$end$
$$if$  PSW.1
    enable();
$$end$
}

void main(void)
{
 Init_SingleTrans_PTS_$%dPTS_VECTOR$();
 while(1);
} 
 
/*
   When the PTS cycle is finished it will generate an end-of-pts
   interrupt.

   If the specific peripheral design screen is not used for the
   interrupt routine, then the following can be used for a template.

#pragma interrupt(End_of_PTS@@INT_VECTOR@=@@INT_VECTOR@)
void End_of_PTS@@INT_VECTOR@(void)
{
   User Code
}
*/
##80C196NP PTS_Block#
##80C196NU PTS_Block#
$$ifp$80c196np
#pragma model(NP)
#include <80c196np.h>
$$end$
$$ifp$80c196nu
#pragma model(NU)
#include <80c196nu.h>
$$end$
#define   PTS_BLOCK_BASE      0x0$%XPTS_VECTOR * 8 + 0x380$

/*
   Create typedef template for the block transfer control
   block.
*/
typedef struct BlockTran_ptscb_t {
                             unsigned char  ptscount;
                             unsigned char  ptscon;
                             void  *ptssrc;
                             void  *ptsdst;
                             unsigned char ptsblock;
                             unsigned char unused;
                         } BlockTran_ptscb;

/*
   This locates the PTS Block mode control block in register
   ram.  This control block may be located at any quad-word
   boundary in register space.
*/
BlockTran_ptscb Block_CB_$%dPTS_VECTOR$;
#pragma locate(Block_CB_$%dPTS_VECTOR$=PTS_BLOCK_BASE)

/*
   The PTS vector must contain the address of the PTS control
   block.
*/
#pragma pts(Block_CB_$%dPTS_VECTOR$=0x$%XPTS_VECTOR$)

/*
   The following code is an example of a PTS control block
   initialization sequence.
*/
void Init_BlockTrans_PTS_$%dPTS_VECTOR$(void)
{
    Block_CB_$%dPTS_VECTOR$.ptscount = 0x@@PTSCOUNT@;
    Block_CB_$%dPTS_VECTOR$.ptssrc   = (void *)0x@@PTSSRC@;
    Block_CB_$%dPTS_VECTOR$.ptsdst   = (void *)0x@@PTSDST@;
    Block_CB_$%dPTS_VECTOR$.ptscon   = 0x$$PTSCON$;
    Block_CB_$%dPTS_VECTOR$.ptsblock = 0x@@PTSBLOCK@;
$$if$ PTSSEL_ENABLE