hl196.txt

mcs51,2051,x86系列MCU

HILITES.TXT
#Sync 80C196NT#
#Sync 80C196NQ#
#Sync 80C196KT#
#Sync 80C196KR#
#Sync 80C196KQ#
#Sync 80C196JR#
#Sync 80C196JQ#
#Sync 80C196JT#
Synchronous Serial Port\n
 - Up to 2 Mbaud synchronous communications @ 16 MHz\n
 - Two separate channels (with separate CLK and DATA pins)\n
 - Five different channel configurations (slave/master)\n
 - Designed for use with the PTS\n
 - Perfect for interprocessor communications\n
 - Dedicated baud-rate generator\n
#Serial 80C196NT#
#Serial 80C196NP#
#Serial 80C196NQ#
#Serial 80C196KT#
#Serial 80C196KR#
#Serial 80C196KQ#
#Serial 80C196JQ#
#Serial 80C196JR#
#Serial 80C196JT#
Serial Port\n
 - Full duplex support\n
 - One synchronous and three asynchronous modes\n
 - Framing and parity error detection\n
 - Independent 15-bit baud-rate generator for generation of any baud rate\n
 - Interrupt on transmissions or receptions\n
 - Use with the PTS for block transmissions/receptions\n
#Serial 80C196NU#
#Serial 80C296SA#
Serial Port\n
 - Full duplex support\n
 - One synchronous and three asynchronous modes\n
 - Framing and parity error detection\n
 - Independent 15-bit baud-rate generator for generation of any baud rate\n
 - Baud-rate generator prescaler for 80C196NP compatibility\n
 - Interrupt on transmissions or receptions\n
 - Use with the PTS for block transmissions/receptions\n
#Clock 80C196NT#
#Clock 80C196NQ#
#Clock 80C196KT#
#Clock 80C196KR#
#Clock 80C196KQ#
#Clock 80C196JQ#
#Clock 80C196JR#
#Clock 80C196JT#
Clock\n
 - Tested from 8 to 20 MHz\n
 - Static design, allows operation below 1 Hz\n
 - External CLKOUT pin @ 1/2 clock frequency\n
#Clock 80C196NP#
Clock\n
 - Tested from 8 to 25 MHz\n
 - Static design, allows operation below 1 Hz\n
 - External CLKOUT pin @ 1/2 clock frequency\n
#Clock 80C196NU#
#Clock 80C296SA#
Clock\n
 - Tested from 8 to 50 MHz\n
 - Static design, allows operation below 1 Hz\n
 - External CLKOUT pin @ 1/2 clock frequency\n
#Comp 80C196NT#
#Comp 80C196NQ#
#Comp 80C196KT#
#Comp 80C196KR#
#Comp 80C196KQ#
#Comp 80C196JQ#
#Comp 80C196JR#
#Comp 80C196JT#
Software Timer Compare\n
 - Two separate compare-only channels for software timer functions\n
 - Coupled with output pins (EPA8/EPA9) for 16-bit PWM functions\n
 - Start A/Ds, generate interrupts, reset timers, or toggle pins\n
#Timer 80C196NT#
#Timer 80C196NP#
#Timer 80C196NQ#
#Timer 80C196KT#
#Timer 80C196KR#
#Timer 80C196KQ#
#Timer 80C196JQ#
#Timer 80C196JR#
#Timer 80C196JT#
Flexible Timer Counters\n
 - Two 16-bit timers\n
 - Programmable three-bit prescaler (divide by 1 to divide by 64)\n
 - Clocked internally or externally\n
 - EPA can capture and reset timers\n
 - Timers count up or down\n
 - Quadrature counting mode available\n
#Timer 80C196NU#
#Timer 80C296SA#
Flexible Timer Counters\n
 - Two 16-bit timers\n
 - Programmable three-bit prescaler (divide by 1 to divide by 128)\n
 - Clocked internally or externally\n
 - EPA can capture and reset timers\n
 - Timers count up or down\n
 - Quadrature counting mode available\n
#EPA 80C196NT#
#EPA 80C196NQ#
#EPA 80C196KT#
#EPA 80C196KR#
#EPA 80C196KQ#
Event Processor Array\n
 - Ten-channel Event Processor Array\n
 - Used for high-speed input capture or output compare\n
 - 250 ns resolution @ 16 MHz\n
 - Start A/Ds, generate interrupts, reset timers, or toggle pins\n
 - Captures rising, falling, or both edges\n
 - Detects input overflows\n
#EPA 80C196NP#
#EPA 80C196NU#
#EPA 80C296SA#
Event Processor Array\n
 - Four-channel Event Processor Array\n
 - Used for high-speed input capture or output compare\n
 - 250 ns resolution @ 16 MHz\n
 - Start A/Ds, generate interrupts, reset timers, or toggle pins\n
 - Captures rising, falling, or both edges\n
 - Detects input overflows\n
#EPA 80C196JQ#
#EPA 80C196JR#
#EPA 80C196JT#
Event Processor Array\n
 - Six-channel Event Processor Array\n
 - Used for high-speed input capture or output compare\n
 - 250 ns resolution @ 16 MHz\n
 - Start A/Ds, generate interrupts, reset timers, or toggle pins\n
 - Captures rising, falling, or both edges\n
 - Detects input overflows\n
#AD 80C196NT#
#AD 80C196NQ#
Analog-to-Digital Converter\n
 - Four channels, 8- or 10-bit resolution\n
 - Threshold-detection mode\n
 - Sample and hold\n
 - Less than 16 us conversion time\n
 - Programmable sample and conversion times\n
 - Convert on analog GND and VREF for error correction\n
 - PTS mode for single- or multi-channel scanning\n
#AD 80C196KT#
#AD 80C196KR#
#AD 80C196KQ#
Analog-to-Digital Converter\n
 - Eight channels, 8- or 10-bit resolution\n
 - Threshold-detection mode\n
 - Sample and hold\n
 - Less than 16 us conversion time\n
 - Programmable sample and conversion times\n
 - Convert on analog GND and VREF for error correction\n
 - PTS mode for single- or multi-channel scanning\n
#AD 80C196JQ#
#AD 80C196JR#
#AD 80C196JT#
Analog-to-Digital Converter\n
 - Six channels, 8- or 10-bit resolution\n
 - Threshold-detection mode\n
 - Sample and hold\n
 - Less than 16 us conversion time\n
 - Programmable sample and conversion times\n
 - Convert on analog GND and VREF for error correction\n
 - PTS mode for single- or multi-channel scanning\n
#CPU 80C196NT#
#CPU 80C196NQ#
Central Processing Unit\n
 - High-performance CPU\n
 - 24-bit program counter\n
 - Supports three-operand instructions\n
 - Performs 16 x 16 multiply in 1.75 us @ 16 MHz\n
 - Performs 32 / 16 divide in 3.0 us @ 16 MHz\n
 - Register-to-register architecture\n
#CPU 80C196NP#
Central Processing Unit\n
 - High-performance CPU\n
 - 24-bit program counter\n
 - Supports three-operand instructions\n
 - Performs 16 x 16 multiply in 1.12 us @ 25 MHz\n
 - Performs 32 / 16 divide in 1.92 us @ 25 MHz\n
 - Register-to-register architecture\n
#CPU 80C196NU#
#CPU 80C296SA#
Central Processing Unit\n
 - Functionally compatible with the 80C196NP MCU\n
 - High-performance CPU\n
 - 24-bit program counter\n
 - Supports three-operand instructions\n
 - Performs 16 x 16 multiply in 640 ns @ 50 MHz\n
 - Performs 32 / 16 divide in 960 ns @ 50 MHz\n
 - Register-to-register architecture\n
#CPU 80C196KT#
#CPU 80C196KR#
#CPU 80C196KQ#
#CPU 80C196JQ#
#CPU 80C196JR#
#CPU 80C196JT#
Central Processing Unit\n
 - High-performance CPU\n
 - Supports three-operand instructions\n
 - Performs 16 x 16 multiply in 1.75 us @ 16 MHz\n
 - Performs 32 / 16 divide in 3.0 us @ 16 MHz\n
 - Register-to-register architecture\n
#WDT 80C196NT#
#WDT 80C196NP#
#WDT 80C196NU#
#WDT 80C296SA#
#WDT 80C196NQ#
#WDT 80C196KT#
#WDT 80C196KR#
#WDT 80C196KQ#
#WDT 80C196JQ#
#WDT 80C196JR#
#WDT 80C196JT#
Watchdog Timer\n
 - 16-bit timer\n
 - Allows recovery from system upsets\n
 - Resets processor on overflow\n
 - Programmable to remain on or off after reset\n
 - Increases system reliability\n
#DATA 80C196NT#
RAM\n
 - 512 bytes of internal RAM for code and/or data\n
 - 1000 bytes of register RAM\n
 - 1 Mbyte of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196NP#
#DATA 80C196NU#
RAM\n
 - 1000 bytes of register RAM\n
 - 1 Mbyte of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C296SA#
 - 1000 bytes of register RAM\n
 - 6 Mbyte of addressability to external RAM/ROM   EDIT_ME!!!!!!.....\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196KT#
RAM\n
 - 512 bytes of internal RAM for code and/or data\n
 - 1000 bytes of register RAM\n
 - 64 Kbytes of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196NQ#
RAM\n
 - 128 bytes of internal RAM for code and/or data\n
 - 360 bytes of register RAM\n
 - 1 Mbyte of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196KR#
#DATA 80C196JR#
RAM\n
 - 256 bytes of internal RAM for code and/or data\n
 - 488 bytes of register RAM\n
 - 64 Kbytes of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196JT#
RAM\n
 - 512 bytes of internal RAM for code and/or data\n
 - 1 Kbytes of register RAM\n
 - 64 Kbytes of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#DATA 80C196KQ#
#DATA 80C196JQ#
RAM\n
 - 128 bytes of internal RAM for code and/or data\n
 - 360 bytes of register RAM\n
 - 64 Kbytes of addressability to external RAM/ROM\n
 - Fast context switching\n
 - Register-to-register architecture\n
 - Flexible orthogonal structure\n
 - Reduces system chip count\n
 - Perfect for boot-loader applications\n
#IO 80C196NT#
#IO 80C196NP#
#IO 80C196NU#
#IO 80C296SA#
#IO 80C196NQ#
#IO 80C196KT#
#IO 80C196KR#
#IO 80C196KQ#
I/O Unit\n
 - 56 flexible I/O port pins\n
 - Direction register\n
 - Multiplexer control pin register\n
 - Latch register for direct AND, OR, XOR functions\n
 - Pin state register for direct pin state monitoring\n
#IO 80C196JR#
#IO 80C196JT#
#IO 80C196JQ#
I/O Unit\n
 - 41 flexible I/O port pins\n
 - Direction register\n
 - Multiplexer control pin register\n
 - Latch register for direct AND, OR, XOR functions\n
 - Pin state register for direct pin state monitoring\n
#BIU 80C196NT#
#BIU 80C196NP#
#BIU 80C196NU#
#BIU 80C196NQ#
Bus Interface Unit\n
 - 1 Mbyte addressability (20-bit external address bus)\n
 - READY control for slower memories (0, 1, 2, 3 and infinite wait states)\n
 - On-the-fly 8- or 16-bit buswidth control\n
 - WR#/BHE or WRL#/WRH# for flexible write functions\n
 - Control pins can function as I/O pins when not in use\n
 - Enhanced bus timing modes for faster operation with slower memories\n
 - HOLD/HLDA protocol\n
#BIU 80C296SA#
 - 6 Mbyte addressability (20-bit external address bus)           EDIT_ME!!!!!!.... \n
 - READY control for slower memories (0, 1, 2, 3 and infinite wait states)\n
 - On-the-fly 8- or 16-bit buswidth control\n
 - WR#/BHE or WRL#/WRH# for flexible write functions\n
 - Control pins can function as I/O pins when not in use\n
 - Enhanced bus timing modes for faster operation with slower memories\n
 - HOLD/HLDA protocol\n
#BIU 80C196KT#
#BIU 80C196KR#
#BIU 80C196KQ#
Bus Interface Unit\n
 - 64 Kbyte addressability (16-bit external address bus)\n
 - READY control for slower memories (0, 1, 2, 3 and infinite wait states)\n
 - On-the-fly 8- or 16-bit buswidth control\n
 - WR#/BHE or WRL#/WRH# for flexible write functions\n
 - Control pins can function as I/O pins when not in use\n
 - HOLD/HLDA protocol\n
#BIU 80C196JQ#
#BIU 80C196JR#
#BIU 80C196JT#
Bus Interface Unit\n
 - WR#/BHE or WRL#/WRH# for flexible write functions\n
 - Control pins can function as I/O pins when not in use\n
 - 64 Kbyte addressability (16-bit external address bus)\n
 - 8- or 16-bit buswidth control\n
#CODE 80C196NT#
#CODE 80C196NP#
ROM/EPROM\n