pe196.rd1

mcs51,2051,x86系列MCU

The High-Speed Output (HSO) module triggers events at specified times using
either Timer 1 or Timer 2 as the time reference.
#HSO? 80C196K? 210#
#HSO? 80C19? 210#
#HSO? 80C196K? 211#
#HSO? 80C19? 211#
Determine whether the Event time value is an Absolute timer value or a Relative
value offset from the current reference timer value.
#HSO? 80C196K? 220#
#HSO? 80C19? 220#
Enter the HSO Event time.

The contents of the HSO_TIME and HSO_COMMAND registers together define each
HSO event.  The HSO_TIME register specifies the time at which an HSO command
is to be executed.  The value in HSO_TIME can be either an Absolute timer
value (Event Time Relation = Absolute) or a value that is offset from the
current timer value (Event Time Relation = Relative).
#ICU 80C19? 100#
#ICU 80C196K? 100#
#ICU 80C196K? 500#
#ICU 80C19? 500#
Select the configure option to enable or disable the individual interrupts.

The Nonmaskable, Unimplemented Opcode, and Trap interrupts are always
enabled.

Check the "Enable Global Interrupts" box to set the global interrupt bit in
the Program Status Word. This bit is set by the EI instruction and cleared by
the DI instruction.
#ICU 80C196K? 600#
#ICU 80C19? 600#
#ICU 80C196K? 601#
#ICU 80C19? 601#
Select either the EXTINT or P0.7 pin as the source for the External interrupt.

The External 1 interrupt uses the EXTINT pin as its interrupt source.
Therefore when the EXTINT pin is selected as the interrupt source for the
External interrupt the External 1 interrupt should be disabled.
#ICU 80C196K? 602#
#ICU 80C19? 602#
Check this box to enable the External interrupt.

Enabling the interrupt sets the corresponding bit in the interrupt mask
register.
#ICU 80C196K? 603#
#ICU 80C19? 603#
Check this box to enable the External 1 interrupt.

Enabling the interrupt sets the corresponding bit in the interrupt mask
register.
#ICU 80C196K? 701#
#ICU 80C19? 701#
#ICU 80C196K? 702#
#ICU 80C19? 702#
Determine whether to enable or disable the interrupt.

Enabling an interrupt sets its corresponding bit in the interrupt mask
registers.

Disabling an interrupt clears its corresponding bit in the interrupt mask
registers.
#ICU 80C196K? 703#
#ICU 80C19? 703#
Enter the name of the desired Interrupt Service Routine.
#PTS 80C196K? 400#
#PTS 80C196K? 102#
The configure option allows you to select the PTS mode for each interrupt.

Check the "Enable PTS" box to set the PTS enable bit in the Program Status
Word.  This bit is set by the EPTS instruction and cleared by the DPTS
instruction.
#PTS 80C196K? 607#
#PTS 80C196K? 651#
Enter the PTS source address.

In single transfer mode, the PTS moves a byte or word from the location pointed 
to by the PTS source register to the location pointed to by the PTS destination
register.

In block transfer mode, the PTS moves a block of bytes or words from the
location pointed to by the PTS source register to the location pointed to by
the PTS destination register.
#PTS 80C196K? 604#
#PTS 80C196K? 650#
Enter the PTS destination address.

In single transfer mode, the PTS moves a byte or word from the location pointed 
to by the PTS source register to the location pointed to by the PTS destination
register.

In block transfer mode, the PTS moves a block of bytes or words from the
location pointed to by the PTS source register to the location pointed to by
the PTS destination register.
#PTS 80C196K? 606#
#PTS 80C196K? 655#
#PTS 80C196K? 801#
#PTS 80C196K? 751#
#PTS 80C196K? 701#
Enter the desired number of PTS cycles.

The number of cycles should be a number from 1 to 256. The PTS decrements the
count prior to each cycle; therefore, an entry of 0 would cause the PTS to
perform 256 cycles.
#PTS 80C196K? 656#
Enter the desired number of bytes or words to be transferred in each block.

The number of transfers must be a number from 1-32.
#PTS 80C196K? 608#
#PTS 80C196K? 609#
#PTS 80C196K? 657#
#PTS 80C196K? 658#
Determine whether to transfer bytes or words.
#PTS 80C196K? 605#
#PTS 80C196K? 654#
#PTS 80C196K? 700#
#PTS 80C196K? 803#
#PTS 80C196K? 753#
Select this option to enable the PTS interrupt.

Enabling the PTS interrupt causes the associated bits in the Interrupt Mask
registers and the PTS Select register to be set.
#PTS 80C196K? 603#
#PTS 80C196K? 653#
Select this option to enable the auto-increment source address feature.

The auto-increment source address feature causes the PTS to increment the
source address at the end of each PTS transfer.

In single transfer mode, when the auto-increment source address is enabled, the
update source address must also be enabled.
#PTS 80C196K? 602#
#PTS 80C196K? 652#
Select this option to enable the auto-increment destination address feature.

The auto-increment destination address feature causes the PTS to increment the
destination address at the end of each PTS transfer.

In single transfer mode, when the auto-increment destination address is enabled,
the update destination address must also be enabled.
#PTS 80C196K? 611#
#PTS 80C196K? 660#
#PTS 80C196K? 804#
Select this option to enable the update source address feature.

The update source address feature causes the PTS to increment the source
address at the end of each PTS cycle.

In single transfer mode, when the update source address is enabled, the
auto-increment source address must also be enabled.
#PTS 80C196K? 610#
#PTS 80C196K? 659#
Select this option to enable the update destination address feature.

The update destination address feature causes the PTS to increment the
destination address at the end of each PTS cycle.

In single transfer mode, when the update destination address is enabled, the
auto-increment destination address must also be enabled.
#PTS 80C196K? 702#
Select this option to enable the Auto-increment feature.

When the auto-increment feature is enabled, the register that points to the table
of conversion commands and results (PTS_S/D) retains its final value.

When the auto-increment feature is disabled, the PTS causes the PTS_S/D register
to revert to the value that existed at the beginning of the PTS cycle.
#PTS 80C196K? 703#
Enter the name of the table of A/D conversion commands and results.
#PTS 80C196KC 754#
Selecting this option caused the PTSDST register to retain its final value at
the end of the PTS cycle.
#PTS 80C196K? 750#
Enter the name of the table that the PTS will write the contents of the HSI
FIFO to.
#PTS 80C196K? 800#
Enter the name of the table that the PTS will load the HSO CAM from.
#PTS 80C196K? 802#
#PTS 80C196K? 752#
Select the number of HSI FIFO blocks to be transferred to memory during each
PTS cycle.
#IO 80C19? 100#
#IO 80C196K? 100#
#IO 80C19? 101#
#IO 80C196K? 101#
#IO 80C19? 110#
#IO 80C196K? 110#
#IO 80C19? 111#
#IO 80C196K? 111#
#IO 80C196K? 180#
#IO 80C196K? 181#
#IO 80C196K? 190#
#IO 80C196K? 191#
#IO 80C196K? 200#
#IO 80C196K? 201#
#IO 80C196K? 210#
#IO 80C196K? 211#
#IO 80C196K? 220#
#IO 80C196K? 221#
#IO 80C196K? 230#
#IO 80C196K? 231#
#IO 80C196K? 240#
#IO 80C196K? 241#
#IO 80C196K? 250#
#IO 80C196K? 251#
Determine whether to configure this quasi-bidirectional port pin as an input or
an output pin.

Quasi-bidirectional pins can be used as input and/or output pins (without the
need for direction control logic).  These pins output a strong low value or a
weak high value.  The weak high value can be externally overridden, providing
an input function.
#IO 80C19? 112#
#IO 80C196K? 112#
Select this option to configure the P2.6 pin as the T2UP-DN pin.

T2UP-DN is an active-high input that controls the direction of the Timer 2
counter.  When T2UP-DN is high, Timer 2 counts down; when T2UP-DN is low,
Timer 2 counts up.  Bit 1 in the IOC2 register enables the Timer 2 up/down
count feature.
#IO 80C19? 120#
#IO 80C196K? 120#
#IO 80C19? 170#
#IO 80C196K? 170#
Select this option to configure the port pin as a standard output pin.

An output pin consists of port latch and pin driver logic.  Output port pins
do not have sample and read buffer circuitry.  When an output pin is read, its
value is undefined and should be masked.
#IO 80C19? 130#
#IO 80C196K? 130#
#IO 80C19? 140#
#IO 80C196K? 140#
#IO 80C19? 150#
#IO 80C196K? 150#
#IO 80C19? 160#
#IO 80C196K? 160#
Select the option to configure the port pin as a standard input pin.

Any port pin defined as an input can only be read.  Any write operation to the
pin is ignored (or is not possible).  Input port pins have no output drivers.
The input leakage of these pins is very low, as is their capacitive loading.
#IO 80C19? 121#
#IO 80C196K? 121#
Select this option to configure pin P2.5 as the PWM0 output pin.

Port 2.5 can be enabled as the PWM output by setting IOC1.0.  The duty cycle
of the PWM is determined by the value loaded into the PWM0_CONTROL register.
#IO 80C19? 131#
#IO 80C196K? 131#
Select this option to configure pin P2.4 as the T2RST pin.

A rising edge on the T2RST pin will reset Timer 2.  The external reset
function is enabled by setting IOC0.3.  T2RST is enabled as the reset source
by clearing IOC0.5.
#IO 80C19? 141#
#IO 80C196K? 141#
Select this option to configure the P2.3 pin as the T2CLK pin.

The T2CLK pin is the Timer 2 clock input or the serial baud rate generator
input.
#IO 80C19? 151#
#IO 80C196K? 151#
Select this option to configure the P2.2 pin as the EXTINT pin.

A positive transition on the EXTINT pin will generate an external interrupt.
EXTINT is selected as the external interrupt source by clearing IOC1.1.
#IO 80C19? 161#
#IO 80C196K? 161#
Select this option to configure the P2.1 pin as the RXD pin.

The Serial Port Receive pin is used for serial port reception. The RXD
function is enabled by setting SPCON.3.  In Mode 0, the pin functions as input
or output data.
#IO 80C19? 171#
#IO 80C196K? 171#
Select this option to configure the P2.0 pin as the TXD pin.

The TXD pin is used for serial port transmission in Modes 1, 2 and 3.  The TXD
function is enabled by setting IOC1.5.  In Mode 0, the pin is used as the
serial clock output.
#IO 80C196K? 182#
Select this option to configure the P1.7 pin as the HOLD# pin.

Bus Hold is an active-low input that is used to request control of the bus.
It is enabled by setting WSR.7.
#IO 80C196K? 192#
Select this option to configure the P1.6 pin as the HLDA# pin.

Bus Hold acknowledge is an active-low output that indicates that the processor
has released the bus as a result of another device asserting HOLD#.
#IO 80C196K? 202#
Select this option to configure the P1.5 pin as the BREQ# pin.

Bus Request is an active-low output signal that is asserted during a HOLD cycle
when the bus controller has a pending external memory cycle.
#IO 80C196K? 212#
Select this option to configure pin P1.4 as the PWM2 output pin.

Pin 1.4 can be enabled as the PWM output by setting IOC3.3.  The duty cycle
of the PWM is determined by the value loaded into the PWM2_CONTROL register.
#IO 80C196K? 222#
Select this option to configure pin P1.3 as the PWM1 output pin.

Pin 1.3 can be enabled as the PWM output by setting IOC3.2.  The duty cycle
of the PWM is determined by the value loaded into the PWM1_CONTROL register.
#WDT 80C196?? 100#
The Watchdog register must be cleared within every 64K state times to hold off
a Watchdog Timer reset.
#Serial 80C196K? 30022#
#Serial 80C19? 30022#
#AD 80C196K? 30022#
#AD 80C19? 30022#
Enter the desired frequency in MHz.
#