bcdadder.vhd

来自「2008年北京市大学生电子设计竞赛程序源代码[测频率」· VHDL 代码 · 共 26 行

Library ieee;  
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity bcdadder is  
Port(  a,b : in  std_logic_vector(3 downto 0);
        ci : in std_logic;
    result : out std_logic_vector(3 downto 0);
        co : out std_logic );
End bcdadder;
Architecture Na of bcdadder is 
constant adjnum : integer:=6;               
signal binadd : std_logic_vector(4 downto 0);
signal   re: std_logic_vector(4 downto 0); 
Begin
 binadd<=('0'&a)+('0'&b)+ci;             
process(binadd)           
variable tmp: integer  range 0 to 6; 
begin
if binadd>9 then    tmp:=adjnum;  else   tmp:=0;   end if;
re<= binadd+tmp;
result<=re(3 downto 0);
co<=re(4);
end process;
End Na;