clk_dis.vhd

2008年北京市大学生电子设计竞赛程序源代码[测频率

--------------------------------------------------------------------------
---clock of display 200Hz---
--modify counter to control clk_out
--
--2008.5.6 by Shaolong-Liu
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY clk_dis IS
    PORT(
        clk             : IN    STD_LOGIC;
        clk_out         : OUT   STD_LOGIC
         );
END clk_dis;

ARCHITECTURE fclk OF clk_dis IS
     
    signal counter    : std_logic_vector(5 downto 0);
    signal clk_d      : std_logic;    
BEGIN

clk_out <= clk_d;

process(clk)
	begin
		if rising_edge(clk) then
			counter<=counter+1;
            if counter=40 then
                counter<="000000";
				clk_d<=not clk_d;
            end if;
        end if;
end process;

end;