onehz_clk.vhd.bak

2008年北京市大学生电子设计竞赛程序源代码[测频率

--------------------------------------------------------------------------
--clock division
--modify counter to control clk_out
--
--2008.4.14 by wangshan
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY onehz_clk IS
    PORT(
        clk             : IN    STD_LOGIC;
        clk_out         : OUT   STD_LOGIC
         );
END onehz_clk;

ARCHITECTURE fclk OF onehz_clk IS
     
    signal counter    : std_logic_vector(24 downto 0);
    signal clk_d      : std_logic;    
BEGIN

clk_out <= clk_d;

process(clk)
	begin
		if rising_edge(clk) then
			counter<=counter+1;
            if counter=8000000 then
                counter<="0000000000000000000000000";
				clk_d<=not clk_d;
            end if;
        end if;
end process;

end;