df.vhd

2008年北京市大学生电子设计竞赛程序源代码[测频率

library ieee;
use ieee.std_logic_1164.all;

entity df is
port
(
  clk:      in std_logic;
  D:        in std_logic_vector(7 downto 0);
  Q:        out std_logic_vector(7 downto 0)
);
end;

architecture a of df is
signal sig_save: std_logic_vector(7 downto 0);
begin

process(clk)

begin
if clk'event and clk='1' then
sig_save<=D;
end if;
Q<=sig_save;

end process;
end;