d_fre.vhd

来自「2008年北京市大学生电子设计竞赛程序源代码[测频率」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;

entity d_fre is
port
(
  clk:      in std_logic;
  D:        in std_logic;
  Q:        out std_logic
);
end;

architecture d1 of d_fre is
--signal sig_save:      std_logic;

begin

process(clk)
begin
 if clk'event and clk='1' then
     Q<=D;
 end if;
 --Q<=sig_save;

end process;
end;