ad0820.map.rpt

2008年北京市大学生电子设计竞赛程序源代码[测频率

; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |ad0820|frequence:inst9|r_2[0] ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |ad0820|frequence:inst9|r_1[3] ;
; 16:1               ; 7 bits    ; 70 LEs        ; 14 LEs               ; 56 LEs                 ; Yes        ; |ad0820|sinA:inst7|outbuff[0]  ;
; 18:1               ; 4 bits    ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |ad0820|display:inst3|LED[0]   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon May 26 19:45:08 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ad0820 -c ad0820
Info: Found 2 design units, including 1 entities, in source file findmax.vhd
    Info: Found design unit 1: findmax-behav
    Info: Found entity 1: findmax
Info: Found 2 design units, including 1 entities, in source file clk_division.vhd
    Info: Found design unit 1: clk_division-SYN
    Info: Found entity 1: clk_division
Info: Found 2 design units, including 1 entities, in source file counter24.vhd
    Info: Found design unit 1: counter24-SYN
    Info: Found entity 1: counter24
Info: Found 2 design units, including 1 entities, in source file frequence.vhd
    Info: Found design unit 1: frequence-behav
    Info: Found entity 1: frequence
Info: Found 2 design units, including 1 entities, in source file onehz_clk.vhd
    Info: Found design unit 1: onehz_clk-fclk
    Info: Found entity 1: onehz_clk
Info: Found 2 design units, including 1 entities, in source file bcd.vhd
    Info: Found design unit 1: bcd-behave
    Info: Found entity 1: bcd
Info: Found 2 design units, including 1 entities, in source file clk_dis.vhd
    Info: Found design unit 1: clk_dis-fclk
    Info: Found entity 1: clk_dis
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-behav
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file adc.vhd
    Info: Found design unit 1: adc-behav
    Info: Found entity 1: adc
Info: Found 1 design units, including 1 entities, in source file ad0820.bdf
    Info: Found entity 1: ad0820
Info: Found 2 design units, including 1 entities, in source file clk_half.vhd
    Info: Found design unit 1: clk_half-fclk
    Info: Found entity 1: clk_half
Info: Found 2 design units, including 1 entities, in source file df.vhd
    Info: Found design unit 1: df-a
    Info: Found entity 1: df
Info: Found 2 design units, including 1 entities, in source file d_fre.vhd
    Info: Found design unit 1: d_fre-d1
    Info: Found entity 1: d_fre
Warning: Can't analyze file -- file E:/北邮最终下载程序/5.33/ad0820/keyctr.vhd is missing
Info: Found 2 design units, including 1 entities, in source file Vtab.vhd
    Info: Found design unit 1: Vtab-table
    Info: Found entity 1: Vtab
Info: Elaborating entity "ad0820" for the top level hierarchy
Info: Elaborating entity "adc" for hierarchy "adc:inst"
Warning (10492): VHDL Process Statement warning at adc.vhd(51): signal "data_in" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at adc.vhd(26): inferring latch(es) for signal or variable "data_out", which holds its previous value in one or more paths through the process
Warning (10034): Output port "wr_rdy" at adc.vhd(12) has no driver
Info (10041): Inferred latch for "data_out[0]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[1]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[2]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[3]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[4]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[5]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[6]" at adc.vhd(26)
Info (10041): Inferred latch for "data_out[7]" at adc.vhd(26)
Info: Elaborating entity "clk_half" for hierarchy "clk_half:inst4"
Info: Elaborating entity "df" for hierarchy "df:inst5"
Warning (10492): VHDL Process Statement warning at df.vhd(23): signal "sig_save" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "display" for hierarchy "display:inst3"
Info: Elaborating entity "clk_dis" for hierarchy "clk_dis:inst2"
Info: Elaborating entity "Vtab" for hierarchy "Vtab:inst1"
Warning: Using design file addbcd.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: addbcd-a1
    Info: Found entity 1: addbcd
Info: Elaborating entity "addbcd" for hierarchy "Vtab:inst1|addbcd:ad1"
Warning (10036): Verilog HDL or VHDL warning at addbcd.vhd(18): object "a" assigned a value but never read
Warning: Using design file adder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: adder-a
    Info: Found entity 1: adder
Info: Elaborating entity "adder" for hierarchy "Vtab:inst1|addbcd:ad1|adder:A1"
Warning: Using design file bcdadder.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bcdadder-Na
    Info: Found entity 1: bcdadder
Info: Elaborating entity "bcdadder" for hierarchy "Vtab:inst1|addbcd:ad1|adder:A1|bcdadder:U1"
Warning (10492): VHDL Process Statement warning at bcdadder.vhd(21): signal "re" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at bcdadder.vhd(22): signal "re" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Using design file sinA.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sinA-b
    Info: Found entity 1: sinA
Info: Elaborating entity "sinA" for hierarchy "sinA:inst7"
Info: Elaborating entity "findmax" for hierarchy "findmax:inst10"
Info: Elaborating entity "d_fre" for hierarchy "d_fre:inst8"
Info: Elaborating entity "frequence" for hierarchy "frequence:inst9"
Info: Elaborating entity "onehz_clk" for hierarchy "onehz_clk:inst6"
Warning (14130): Reduced register "sinA:inst7|da1_8[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sinA:inst7|da1_8[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sinA:inst7|da1_8[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sinA:inst7|da1_4[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sinA:inst7|da1_4[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "sinA:inst7|da1_2[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Vtab:inst1|t2[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Vtab:inst1|t2[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Vtab:inst1|t2[8]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "Vtab:inst1|t2[9]" with stuck data_in port to stuck value GND