mport1.h

SMDK2440 boot code, base on vivi

#include "config.h"
#include "s3c2410.h"

/*
 * Memory map
 */
#include "sizes.h"

/* Porocessor memory map */
#define ROM_BASE0		0x00000000      /* base address of rom bank 0 */
#define ROM_BASE1		0x08000000      /* base address of rom bank 1 */
#define DRAM_BASE0		0x30000000      /* base address of dram bank 0 */
#define DRAM_BASE1		0x38000000	/* base address of dram bank 1 */

/* Flash */
#define FLASH_BASE		ROM_BASE0
#define FLASH_SIZE		SZ_64M
#define FLASH_UNCACHED_BASE	0x10000000	/* to mapping flash memory */
#define FLASH_BUSWIDTH		2
/* ROM */
#define VIVI_ROM_BASE		0x00000000
#define VIVI_PRIV_ROM_BASE	0x01FC0000
/* RAM */
#define DRAM_BASE		DRAM_BASE0
#define DRAM_SIZE		SZ_32M
/* SRAM */
#define SRAM_BASE		0x38000000

#define MTD_PART_SIZE		SZ_16K
#define MTD_PART_OFFSET		0x00000000
#define PARAMETER_TLB_SIZE	SZ_16K
#define PARAMETER_TLB_OFFSET	0x00004000
#define LINUX_CMD_SIZE		SZ_16K
#define LINUX_CMD_OFFSET	0x00008000
#define VIVI_PRIV_SIZE		(MTD_PART_SIZE + PARAMETER_TLB_SIZE + LINUX_CMD_SIZE)


/* RAM */
#define VIVI_RAM_SIZE		SZ_1M
#define VIVI_RAM_BASE		(DRAM_BASE + DRAM_SIZE - VIVI_RAM_SIZE)
#define HEAP_SIZE		SZ_1M
#define HEAP_BASE		(VIVI_RAM_BASE - HEAP_SIZE)
#define MMU_TABLE_SIZE		SZ_16K
#define MMU_TABLE_BASE		(HEAP_BASE - MMU_TABLE_SIZE)
#define VIVI_PRIV_RAM_BASE	(MMU_TABLE_BASE - VIVI_PRIV_SIZE)
#define STACK_SIZE		SZ_32K
#define STACK_BASE		(VIVI_PRIV_RAM_BASE - STACK_SIZE)
#define RAM_SIZE		(STACK_BASE - DRAM_BASE)
#define RAM_BASE		DRAM_BASE

/*
 * Architecture magic and machine type
 */
#define MACH_TYPE		265	
#define VIVI_MAGIC		(0x43090000 | MACH_TYPE)

/*
 * 扁鸥 殿殿
 */
#define UART_BAUD_RATE		115200

#define FIN			12000000

/*
 * CPU 饭瘤胶磐 汲沥 蔼甸
 */

/* initial values for DRAM */
#define vBWSCON			0x02111100
#define vBANKCON0		0x00000700  /* NAND flash */
#define vBANKCON1		0x00003ef0  /* K6F1008V2C SRAM - 8bit */
#define vBANKCON2		0x00000700
#define vBANKCON3		0x00003ef0  /* MSM9842 voice IC - 16bit */
#define vBANKCON4		0x00000700
#define vBANKCON5		0x00000700
#define vBANKCON6		0x00018005
#define vBANKCON7		0x00000700
#define vREFRESH		0x008e0459
#define vBANKSIZE		0xb2
#define vMRSRB6			0x30
#define vMRSRB7			0x30

#define vLOCKTIME		0x00ffffff	/* It's a default value */
#define vCLKCON			0x0000fff8	/* It's a default value */
#define vCLKDIVN		0x3		/* FCLK:HCLK:PCLK = 1:2:4 */
#define MDIV			0xa1
#define PDIV			0x3
#define SDIV			0x1
#define vMPLLCON		((MDIV << 12) | (PDIV << 4) | (SDIV))  /* 202.80 MHz */

/* initial values for serial */
#define vULCON			0x3	/* UART, no parity, one stop bit, 8 bits */
#define vUCON			0x245
#define vUFCON			0x0
#define vUMCON			0x0

/* inital values for GPIOs */
#define vGPACON			0x005e1fff
#define vGPADAT			0x00206000
#define vGPBCON			0x00145455
#define vGPBUP			0x000007ff
#define vGPBDAT			0x00000001
#define vGPCCON			0xaaa056a9
#define vGPCUP			0x000003e1
#define vGPCDAT			0x00000000
#define vGPDCON			0xaaaaaaaa
#define vGPDUP			0x0000ffff
#define vGPDDAT			0x00000000
#define vGPECON			0x41954404
#define vGPEUP			0x0000ffff
#define vGPEDAT			0x00000020
#define vGPFCON			0x00000000
#define vGPFUP			0x000000ff
#define vGPFDAT			0x00000000
#define vGPGCON			0x54000000
#define vGPGUP			0x0000ffff
#define vGPGDAT			0x00000000
#define vGPHCON			0x0015aaa5
#define vGPHUP			0x000007ff
#define vGPHDAT			0x00000000
#define vEXTINT0		0x22222222
#define vEXTINT1		0x22222222
#define vEXTINT2		0x22222222