s3c2410.h

将s3c2410作为usb设备

#define INT_EINT3		(1 << 3)	/* External interrupt 3 */
#define INT_EINT2		(1 << 2)	/* External interrupt 2 */
#define INT_EINT1		(1 << 1)	/* External interrupt 1 */
#define INT_EINT0		(1 << 0)	/* External interrupt 0 */

#define INT_ADC			(1 << 10)
#define INT_TC			(1 << 9)
#define INT_ERR2		(1 << 8)
#define INT_TXD2		(1 << 7)
#define INT_RXD2		(1 << 6)
#define INT_ERR1		(1 << 5)
#define INT_TXD1		(1 << 4)
#define INT_RXD1		(1 << 3)
#define INT_ERR0		(1 << 2)
#define INT_TXD0		(1 << 1)
#define INT_RXD0		(1 << 0)

/* NAND Flash Controller */
#define NAND_CTL_BASE		0x4E000000
#define bINT_CTL(Nb)		__REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oNFCONF			0x00
#define oNFCMD			0x04
#define oNFADDR			0x08
#define oNFDATA			0x0c
#define oNFSTAT			0x10
#define oNFECC			0x14

//RTC(Real Time Controller)
#define RTCBASE(offset)			__REGb(0x57000000 + (offset))
#define RTCCON    						RTCBASE(0x40) //RTC control
#define TICNT     						RTCBASE(0x44) //Tick time count
#define RTCALM    						RTCBASE(0x50) //RTC alarm control
#define ALMSEC    						RTCBASE(0x54) //Alarm second
#define ALMMIN    						RTCBASE(0x58) //Alarm minute
#define ALMHOUR   					RTCBASE(0x5c) //Alarm Hour
#define ALMDATE   					RTCBASE(0x60) //Alarm day      <-- May 06, 2002 SOP
#define ALMMON    						RTCBASE(0x64) //Alarm month
#define ALMYEAR   					RTCBASE(0x68) //Alarm year
#define RTCRST    						RTCBASE(0x6c) //RTC round reset
#define BCDSEC    						RTCBASE(0x70) //BCD second
#define BCDMIN    						RTCBASE(0x74) //BCD minute
#define BCDHOUR   					RTCBASE(0x78) //BCD hour
#define BCDDATE   					RTCBASE(0x7c) //BCD day        <-- May 06, 2002 SOP
#define BCDDAY    						RTCBASE(0x80) //BCD date       <-- May 06, 2002 SOP
#define BCDMON    						RTCBASE(0x84) //BCD month
#define BCDYEAR   					RTCBASE(0x88) //BCD year

/* PWM Timer */
#define bPWM_TIMER(Nb)          __REG(0x51000000 + (Nb))
#define bPWM_BUFn(Nb,x)         bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
/* Registers */
#define TCFG0                	bPWM_TIMER(0x00)
#define TCFG1                     	bPWM_TIMER(0x04)
#define TCON                        	bPWM_TIMER(0x08)
#define TCNTB0                 	bPWM_BUFn(0,0x0)
#define TCMPB0                  	bPWM_BUFn(0,0x4)
#define TCNTO0                  	bPWM_BUFn(0,0x8)
#define TCNTB1                  	bPWM_BUFn(1,0x0)
#define TCMPB1                  	bPWM_BUFn(1,0x4)
#define TCNTO1                  	bPWM_BUFn(1,0x8)
#define TCNTB2                  	bPWM_BUFn(2,0x0)
#define TCMPB2                  	bPWM_BUFn(2,0x4)
#define TCNTO2                  	bPWM_BUFn(2,0x8)
#define TCNTB3                  	bPWM_BUFn(3,0x0)
#define TCMPB3                  	bPWM_BUFn(3,0x4)
#define TCNTO3                  	bPWM_BUFn(3,0x8)
#define TCNTB4                  	bPWM_BUFn(4,0x0)
#define TCNTO4                  	bPWM_BUFn(4,0x4)
/* Fields */
#define fTCFG0_DZONE            Fld(8,16)       /* the dead zone length (= timer 0) */
#define fTCFG0_PRE1             Fld(8,8)        /* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0             Fld(8,0)        /* prescaler value for time 0,1 */
#define fTCFG1_MUX4		Fld(4,16)
/* bits */
#define TCFG0_DZONE(x)          FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x)           FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x)           FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO             (1 << 22)       /* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE           (1 << 21)       /* manual Update TCNTB4 */
#define TCON_4_ONOFF            (1 << 20)       /* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON              (TCON_4_ONOFF*1)
#define COUNT_4_OFF             (TCON_4_ONOFF*0)
#define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
#define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
#define TIMER3_IVT_ON   (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
#define TIMER3_MANUP    (TCON_3_MAN*1)
#define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
#define TIMER3_ON       (TCON_3_ONOFF*1)
#define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
/* macros */
#define GET_PRESCALE_TIMER4(x)	FExtr((x), fTCFG0_PRE1)
#define GET_DIVIDER_TIMER4(x)	FExtr((x), fTCFG1_MUX4)

/*
 * NAND Flash Controller (Page 6-1 ~ 6-8)
 *
 * Register
   NFCONF   NAND Flash Configuration    [word, R/W, 0x00000000]
   NFCMD    NAND Flash Command Set      [word, R/W, 0x00000000]
   NFADDR   NAND Flash Address Set      [word, R/W, 0x00000000]
   NFDATA   NAND Flash Data             [word, R/W, 0x00000000]
   NFSTAT   NAND Flash Status           [word, R, 0x00000000]
   NFECC    NAND Flash ECC              [3 bytes, R, 0x00000000]
 *
 */
#define bNAND_CTL(Nb)	__REG(0x4e000000 + (Nb))
#define NFCONF          bNAND_CTL(0x00)
#define NFCMD       	bNAND_CTL(0x04)
#define NFADDR      	bNAND_CTL(0x08)
#define NFDATA      	__REGb(0x4e000000+0x0c)
#define NFSTAT      	bNAND_CTL(0x10)
#define NFECC0      	bNAND_CTL(0x14)
#define NFECC1      	bNAND_CTL(0x15)
#define NFECC2      	bNAND_CTL(0x16)

#define fNFCONF_TWRPH1   Fld(3,0)
#define NFCONF_TWRPH1    FMsk(fNFCONF_TWRPH1)
#define NFCONF_TWRPH1_0  FInsrt(0x0, fNFCONF_TWRPH1) /* 0 */
#define fNFCONF_TWRPH0   Fld(3,4)
#define NFCONF_TWRPH0    FMsk(fNFCONF_TWRPH0)
#define NFCONF_TWRPH0_3  FInsrt(0x3, fNFCONF_TWRPH0) /* 3 */
#define fNFCONF_TACLS    Fld(3,8)
#define NFCONF_TACLS     FMsk(fNFCONF_TACLS)
#define NFCONF_TACLS_0   FInsrt(0x0, fNFCONF_TACLS) /* 0 */
#define fNFCONF_nFCE     Fld(1,11)
#define NFCONF_nFCE      FMsk(fNFCONF_nFCE)
#define NFCONF_nFCE_LOW  FInsrt(0x0, fNFCONF_nFCE) /* active */
#define NFCONF_nFCE_HIGH FInsrt(0x1, fNFCONF_nFCE) /* inactive */
#define fNFCONF_ECC      Fld(1,12)
#define NFCONF_ECC       FMsk(fNFCONF_ECC)
#define NFCONF_ECC_NINIT FInsrt(0x0, fNFCONF_ECC) /* not initialize */
#define NFCONF_ECC_INIT  FInsrt(0x1, fNFCONF_ECC)    /* initialize */
#define fNFCONF_ADDRSTEP Fld(1,13)                 /* Addressing Step */
#define NFCONF_ADDRSTEP  FMsk(fNFCONF_ADDRSTEP)
#define fNFCONF_PAGESIZE Fld(1,14)
#define NFCONF_PAGESIZE  FMsk(fNFCONF_PAGESIZE)
#define NFCONF_PAGESIZE_256  FInsrt(0x0, fNFCONF_PAGESIZE) /* 256 bytes */
#define NFCONF_PAGESIZE_512  FInsrt(0x1, fNFCONF_PAGESIZE) /* 512 bytes */
#define fNFCONF_FCTRL    Fld(1,15)  /* Flash controller enable/disable */
#define NFCONF_FCTRL     FMsk(fNFCONF_FCTRL)
#define NFCONF_FCTRL_DIS FInsrt(0x0, fNFCONF_FCTRL) /* Disable */
#define NFCONF_FCTRL_EN  FInsrt(0x1, fNFCONF_FCTRL) /* Enable */

#define NFSTAT_RnB      (1 << 0)
#define NFSTAT_nFWE     (1 << 8)
#define NFSTAT_nFRE     (1 << 9)
#define NFSTAT_ALE      (1 << 10)
#define NFSTAT_CLE      (1 << 11)
#define NFSTAT_AUTOBOOT (1 << 15)


/*
 * Power Management
 */
#define SPI_CLK		(1 << 18)
#define IIS_CLK		(1 << 17)
#define IIC_CLK		(1 << 16
#define ADC_CLK		(1 << 15)
#define RTC_CLK		(1 << 14)
#define GPIO_CLK	(1 << 13)
#define UART2_CLK	(1 << 12)
#define UART1_CLK	(1 << 11)
#define UART0_CLK	(1 << 10)
#define SDI_CLK		(1 << 9)
#define PWM_CLK		(1 << 8)
#define USBSLAVE_CLK	(1 << 7)
#define USBHOST_CLK	(1 << 6)
#define LCDC_CLK	(1 << 5)
#define NANDCTL_CLK	(1 << 4)
#define SLEEP_ON	(1 << 3)
#define IDLE		(1 << 2)

#define GSTATUS(Nb)	__REG(0x560000AC + (Nb*4))
#define GSTATUS0	GSTATUS(0)
#define GSTATUS1	GSTATUS(1)
#define GSTATUS2	GSTATUS(2)
#define GSTATUS3	GSTATUS(3)
#define GSTATUS4	GSTATUS(4)
#define PMST		GSTATUS2
#define PMSR0		GSTATUS3
#define PMSR1		GSTATUS4
#define PMCTL0		CLKCON
#define PMCTL1		MISCCR
#define SCLKE		(1 << 19)
#define SCLK1		(1 << 18)
#define SCLK0		(1 << 17)
#define USBSPD1		(1 << 13)
#define USBSPD0		(1 << 12)
#define PMST_HWR	(1 << 0)
#define PMST_SMR	(1 << 1)
#define PMST_WDR	(1 << 2)

/*
 * Watch-dog tiemr
 */
#define WTCON		__REG(0x53000000)
#define WTDAT		__REG(0x53000004)
#define WTCNT		__REG(0x53000008)

//{{外部IO中断号
#define	EINT0			0
#define	EINT1			1
#define	EINT2			2
#define	EINT3			3
#define	EINT4			4
#define	EINT5			5
#define	EINT6			6
#define	EINT7			7
#define	EINT8			8
#define	EINT9			9
#define	EINT10		10
#define	EINT11		11
#define	EINT12		12
#define	EINT13		13
#define	EINT14		14
#define	EINT15		15
#define	EINT16		16
#define	EINT17		17
#define	EINT18		18
#define	EINT19		19
#define	EINT20		20
#define	EINT21		21
#define	EINT22		22
#define	EINT23		23
//}}外部IO中断

// PENDING BIT
#define BIT_EINT0      (0x1)
#define BIT_EINT1      (0x1<<1)
#define BIT_EINT2      (0x1<<2)
#define BIT_EINT3      (0x1<<3)
#define BIT_EINT4_7    (0x1<<4)
#define BIT_EINT8_23   (0x1<<5)
#define BIT_NOTUSED6   (0x1<<6)
#define BIT_BAT_FLT    (0x1<<7)
#define BIT_TICK       (0x1<<8)
#define BIT_WDT        (0x1<<9)
#define BIT_TIMER0     (0x1<<10)
#define BIT_TIMER1     (0x1<<11)
#define BIT_TIMER2     (0x1<<12)
#define BIT_TIMER3     (0x1<<13)
#define BIT_TIMER4     (0x1<<14)
#define BIT_UART2      (0x1<<15)
#define BIT_LCD        (0x1<<16)
#define BIT_DMA0       (0x1<<17)
#define BIT_DMA1       (0x1<<18)
#define BIT_DMA2       (0x1<<19)
#define BIT_DMA3       (0x1<<20)
#define BIT_SDI        (0x1<<21)
#define BIT_SPI0       (0x1<<22)
#define BIT_UART1      (0x1<<23)
#define BIT_NOTUSED24  (0x1<<24)
#define BIT_USBD       (0x1<<25)
#define BIT_USBH       (0x1<<26)
#define BIT_IIC        (0x1<<27)
#define BIT_UART0      (0x1<<28)
#define BIT_SPI1       (0x1<<29)
#define BIT_RTC        (0x1<<30)
#define BIT_ADC        (0x1<<31)
#define BIT_ALLMSK     (0xffffffff)

#define BIT_SUB_ALLMSK (0x7ff)
#define BIT_SUB_ADC    (0x1<<10)
#define BIT_SUB_TC     (0x1<<9)
#define BIT_SUB_ERR2   (0x1<<8)
#define BIT_SUB_TXD2   (0x1<<7)
#define BIT_SUB_RXD2   (0x1<<6)
#define BIT_SUB_ERR1   (0x1<<5)
#define BIT_SUB_TXD1   (0x1<<4)
#define BIT_SUB_RXD1   (0x1<<3)
#define BIT_SUB_ERR0   (0x1<<2)
#define BIT_SUB_TXD0   (0x1<<1)
#define BIT_SUB_RXD0   (0x1<<0)