📄 main.lss
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main.elf: file format elf32-littlearmSections:Idx Name Size VMA LMA File off Algn 0 .text 00001ac4 00100000 00100000 00008000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .rodata 000000e4 00101ac4 00101ac4 00009ac4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .data 00000004 00200000 00101ba8 00010000 2**2 CONTENTS, ALLOC, LOAD, DATA 3 .bss 00000014 00200004 00200004 00010004 2**2 ALLOC 4 .int_data 00000000 00204000 00204000 00010004 2**2 CONTENTS, READONLY 5 .comment 0000007e 00000000 00000000 00010004 2**0 CONTENTS, READONLY 6 .debug_aranges 000001a0 00000000 00000000 00010088 2**3 CONTENTS, READONLY, DEBUGGING 7 .debug_pubnames 0000024b 00000000 00000000 00010228 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_info 00001b12 00000000 00000000 00010473 2**0 CONTENTS, READONLY, DEBUGGING 9 .debug_abbrev 00000594 00000000 00000000 00011f85 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_line 00000748 00000000 00000000 00012519 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_frame 00000430 00000000 00000000 00012c64 2**2 CONTENTS, READONLY, DEBUGGING 12 .debug_str 00000163 00000000 00000000 00013094 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_loc 0000003c 00000000 00000000 000131f7 2**0 CONTENTS, READONLY, DEBUGGING 14 .reset 00000000 00000000 00000000 00013233 2**0 CONTENTS, READONLYDisassembly of section .text:00100000 <_startup>://*- If an exception occurs before remap, this would result in an infinite loop.
//*- To ensure if a exeption occurs before start application to infinite loop.
//*------------------------------------------------------------------------------*/
B InitReset /* 0x00 Reset handler */
100000: ea000010 b 100048 <InitReset>00100004 <undefvec>:undefvec:
B undefvec /* 0x04 Undefined Instruction */
100004: eafffffe b 100004 <undefvec>00100008 <swivec>:swivec:
B swivec /* 0x08 Software Interrupt */
100008: eafffffe b 100008 <swivec>0010000c <pabtvec>:pabtvec:
B pabtvec /* 0x0C Prefetch Abort */
10000c: eafffffe b 10000c <pabtvec>00100010 <dabtvec>:dabtvec:
B dabtvec /* 0x10 Data Abort */
100010: eafffffe b 100010 <dabtvec>00100014 <rsvdvec>:rsvdvec:
B rsvdvec /* 0x14 reserved */
100014: eafffffe b 100014 <rsvdvec>00100018 <irqvec>:irqvec:
B IRQ_Handler_Entry /* 0x18 IRQ */
100018: ea000027 b 1000bc <IRQ_Handler_Entry>0010001c <FIQ_Handler_Entry>:fiqvec: /* 0x1c FIQ */
/*------------------------------------------------------------------------------
//*- Function : FIQ_Handler_Entry
//*- Treatments : FIQ Controller Interrupt Handler.
//*- Called Functions : AIC_FVR[interrupt]
//*------------------------------------------------------------------------------*/
FIQ_Handler_Entry:
/*- Switch in SVC/User Mode to allow User Stack access for C code */
/* because the FIQ is not yet acknowledged*/
/*- Save and r0 in FIQ_Register */
mov r9,r0
10001c: e1a09000 mov r9, r0 ldr r0 , [r8, #AIC_FVR]
100020: e5980104 ldr r0, [r8, #260] msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
100024: e321f0d3 msr CPSR_c, #211 ; 0xd3
/*- Save scratch/used registers and LR in User Stack */
stmfd sp!, { r1-r3, r12, lr}
100028: e92d500e stmdb sp!, {r1, r2, r3, ip, lr}
/*- Branch to the routine pointed by the AIC_FVR */
mov r14, pc
10002c: e1a0e00f mov lr, pc bx r0
100030: e12fff10 bx r0
/*- Restore scratch/used registers and LR from User Stack */
ldmia sp!, { r1-r3, r12, lr}
100034: e8bd500e ldmia sp!, {r1, r2, r3, ip, lr}
/*- Leave Interrupts disabled and switch back in FIQ mode */
msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
100038: e321f0d1 msr CPSR_c, #209 ; 0xd1
/*- Restore the R0 ARM_MODE_SVC register */
mov r0,r9
10003c: e1a00009 mov r0, r9
/*- Restore the Program Counter using the LR_fiq directly in the PC */
subs pc,lr,#4
100040: e25ef004 subs pc, lr, #4 ; 0x400100044 <.RAM_TOP>: 100044: 00204000 eoreq r4, r0, r000100048 <InitReset>: .align 0
.RAM_TOP:
.word Top_Stack
InitReset:
/*------------------------------------------------------------------------------
/*- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
/*------------------------------------------------------------------------------*/
.extern AT91F_LowLevelInit
/*- minumum C initialization */
/*- call AT91F_LowLevelInit( void) */
ldr r13,.RAM_TOP /* temporary stack in internal RAM */
100048: e51fd00c ldr sp, [pc, #-12] ; 100044 <.RAM_TOP>/*--Call Low level init function in ABSOLUTE through the Interworking */
ldr r0,=AT91F_LowLevelInit
10004c: e59f00c4 ldr r0, [pc, #196] ; 100118 <.text+0x118> mov lr, pc
100050: e1a0e00f mov lr, pc bx r0
100054: e12fff10 bx r0/*------------------------------------------------------------------------------
//*- Stack Sizes Definition
//*------------------------
//*- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
//*- the vectoring. This assume that the IRQ management.
//*- The Interrupt Stack must be adjusted depending on the interrupt handlers.
//*- Fast Interrupt not requires stack If in your application it required you must
//*- be definehere.
//*- The System stack size is not defined and is limited by the free internal
//*- SRAM.
//*------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
//*- Top of Stack Definition
//*-------------------------
//*- Interrupt and Supervisor Stack are located at the top of internal memory in
//*- order to speed the exception handling context saving and restoring.
//*- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
//*------------------------------------------------------------------------------*/
.EQU IRQ_STACK_SIZE, (3*8*4)
.EQU ARM_MODE_FIQ, 0x11
.EQU ARM_MODE_IRQ, 0x12
.EQU ARM_MODE_SVC, 0x13
.EQU I_BIT, 0x80
.EQU F_BIT, 0x40
/*------------------------------------------------------------------------------
//*- Setup the stack for each mode
//*-------------------------------*/
mov r0,r13
100058: e1a0000d mov r0, sp
/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
10005c: e321f0d1 msr CPSR_c, #209 ; 0xd1/*- Init the FIQ register*/
ldr r8, =AT91C_BASE_AIC
100060: e59f80b4 ldr r8, [pc, #180] ; 10011c <.text+0x11c>
/*- Set up Interrupt Mode and set IRQ Mode Stack*/
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
100064: e321f0d2 msr CPSR_c, #210 ; 0xd2 mov r13, r0 /* Init stack IRQ */
100068: e1a0d000 mov sp, r0 sub r0, r0, #IRQ_Stack_Size
10006c: e2400060 sub r0, r0, #96 ; 0x60/*- Set up Supervisor Mode and set Supervisor Mode Stack*/
msr CPSR_c, #ARM_MODE_SVC
100070: e321f013 msr CPSR_c, #19 ; 0x13 mov r13, r0 /* Init stack Sup */
100074: e1a0d000 mov sp, r0
/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack*/
# Relocate .data section (Copy from ROM to RAM)
LDR R1, =_etext
100078: e59f10a0 ldr r1, [pc, #160] ; 100120 <.text+0x120> LDR R2, =_data
10007c: e59f20a0 ldr r2, [pc, #160] ; 100124 <.text+0x124> LDR R3, =_edata
100080: e59f30a0 ldr r3, [pc, #160] ; 100128 <.text+0x128>00100084 <LoopRel>:LoopRel: CMP R2, R3
100084: e1520003 cmp r2, r3 LDRLO R0, [R1], #4
100088: 34910004 ldrcc r0, [r1], #4 STRLO R0, [R2], #4
10008c: 34820004 strcc r0, [r2], #4 BLO LoopRel
100090: 3afffffb bcc 100084 <LoopRel>
# Clear .bss section (Zero init)
MOV R0, #0
100094: e3a00000 mov r0, #0 ; 0x0 LDR R1, =__bss_start__
100098: e59f108c ldr r1, [pc, #140] ; 10012c <.text+0x12c> LDR R2, =__bss_end__
10009c: e59f208c ldr r2, [pc, #140] ; 100130 <.text+0x130>001000a0 <LoopZI>:LoopZI: CMP R1, R2
1000a0: e1510002 cmp r1, r2 STRLO R0, [R1], #4
1000a4: 34810004 strcc r0, [r1], #4 BLO LoopZI
1000a8: 3afffffc bcc 1000a0 <LoopZI>
ldr lr,=exit
1000ac: e59fe080 ldr lr, [pc, #128] ; 100134 <.text+0x134> ldr r0,=main
1000b0: e59f0080 ldr r0, [pc, #128] ; 100138 <.text+0x138> bx r0
1000b4: e12fff10 bx r0001000b8 <exit>:
.size _startup, . - _startup
.endfunc
/* "exit" dummy added by mthomas to avoid sbrk write read etc. needed
by the newlib default "exit" */
.global exit
.func exit
exit:
b .
1000b8: eafffffe b 1000b8 <exit>001000bc <IRQ_Handler_Entry>: .size exit, . - exit
.endfunc
/*------------------------------------------------------------------------------
//*- Manage exception
//*---------------
//*- This module The exception must be ensure in ARM mode
//*------------------------------------------------------------------------------
//*------------------------------------------------------------------------------
//*- Function : IRQ_Handler_Entry
//*- Treatments : IRQ Controller Interrupt Handler.
//*- Called Functions : AIC_IVR[interrupt]
//*------------------------------------------------------------------------------*/
.global IRQ_Handler_Entry
.func IRQ_Handler_Entry
IRQ_Handler_Entry:
/*- Manage Exception Entry */
/*- Adjust and save LR_irq in IRQ stack */
sub lr, lr, #4
1000bc: e24ee004 sub lr, lr, #4 ; 0x4 stmfd sp!, {lr}
1000c0: e92d4000 stmdb sp!, {lr}
/*- Save SPSR need to be saved for nested interrupt */
mrs r14, SPSR
1000c4: e14fe000 mrs lr, SPSR stmfd sp!, {r14}
1000c8: e92d4000 stmdb sp!, {lr}
/*- Save and r0 in IRQ stack */
stmfd sp!, {r0}
1000cc: e92d0001 stmdb sp!, {r0}
/*- Write in the IVR to support Protect Mode */
/*- No effect in Normal Mode */
/*- De-assert the NIRQ and clear the source in Protect Mode */
ldr r14, =AT91C_BASE_AIC
1000d0: e59fe044 ldr lr, [pc, #68] ; 10011c <.text+0x11c> ldr r0 , [r14, #AIC_IVR]
1000d4: e59e0100 ldr r0, [lr, #256] str r14, [r14, #AIC_IVR]
1000d8: e58ee100 str lr, [lr, #256]
/*- Enable Interrupt and Switch in Supervisor Mode */
msr CPSR_c, #ARM_MODE_SVC
1000dc: e321f013 msr CPSR_c, #19 ; 0x13
/*- Save scratch/used registers and LR in User Stack */
stmfd sp!, { r1-r3, r12, r14}
1000e0: e92d500e stmdb sp!, {r1, r2, r3, ip, lr}
/*- Branch to the routine pointed by the AIC_IVR */
mov r14, pc
1000e4: e1a0e00f mov lr, pc bx r0
1000e8: e12fff10 bx r0/*- Restore scratch/used registers and LR from User Stack*/
ldmia sp!, { r1-r3, r12, r14}
1000ec: e8bd500e ldmia sp!, {r1, r2, r3, ip, lr}
/*- Disable Interrupt and switch back in IRQ mode */
msr CPSR_c, #I_BIT | ARM_MODE_IRQ
1000f0: e321f092 msr CPSR_c, #146 ; 0x92
/*- Mark the End of Interrupt on the AIC */
ldr r14, =AT91C_BASE_AIC
1000f4: e59fe020 ldr lr, [pc, #32] ; 10011c <.text+0x11c> str r14, [r14, #AIC_EOICR]
1000f8: e58ee130 str lr, [lr, #304]
/*- Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r0}
1000fc: e8bd0001 ldmia sp!, {r0}
/*- Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r14}
100100: e8bd4000 ldmia sp!, {lr} msr SPSR_cxsf, r14
100104: e16ff00e msr SPSR_fsxc, lr
/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
ldmia sp!, {pc}^
100108: e8fd8000 ldmia sp!, {pc}^0010010c <AT91F_Default_FIQ_handler>:
.size IRQ_Handler_Entry, . - IRQ_Handler_Entry
.endfunc
/*---------------------------------------------------------------
//* ?EXEPTION_VECTOR
//* This module is only linked if needed for closing files.
//*---------------------------------------------------------------*/
.global AT91F_Default_FIQ_handler
.func AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler:
b AT91F_Default_FIQ_handler
10010c: eafffffe b 10010c <AT91F_Default_FIQ_handler>00100110 <AT91F_Default_IRQ_handler>: .size AT91F_Default_FIQ_handler, . - AT91F_Default_FIQ_handler
.endfunc
.global AT91F_Default_IRQ_handler
.func AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler:
b AT91F_Default_IRQ_handler
100110: eafffffe b 100110 <AT91F_Default_IRQ_handler>00100114 <AT91F_Spurious_handler>: .size AT91F_Default_IRQ_handler, . - AT91F_Default_IRQ_handler
.endfunc
.global AT91F_Spurious_handler
.func AT91F_Spurious_handler
AT91F_Spurious_handler:
b AT91F_Spurious_handler
100114: eafffffe b 100114 <AT91F_Spurious_handler> 100118: 0010013c andeqs r0, r0, ip, lsr r1 10011c: fffff000 swinv 0x00fff000 100120: 00101ba8 andeqs r1, r0, r8, lsr #23 100124: 00200000 eoreq r0, r0, r0 100128: 00200004 eoreq r0, r0, r4 10012c: 00200004 eoreq r0, r0, r4 100130: 00200018 eoreq r0, r0, r8, lsl r0 100134: 001000b8 ldreqh r0, [r0], -r8 100138: 001002b1 ldreqh r0, [r0], -r10010013c <AT91F_LowLevelInit>://* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void)
{
10013c: e1a0c00d mov ip, sp 100140: e92dd800 stmdb sp!, {fp, ip, lr, pc} 100144: e24cb004 sub fp, ip, #4 ; 0x4 100148: e24dd008 sub sp, sp, #8 ; 0x8 int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
10014c: e3a03102 mov r3, #-2147483648 ; 0x80000000 100150: e1a03ac3 mov r3, r3, asr #21 100154: e50b3010 str r3, [fp, #-16] //* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
100158: e3e020ff mvn r2, #255 ; 0xff 10015c: e3a03c01 mov r3, #256 ; 0x100 100160: e5823060 str r3, [r2, #96]
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
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