📄 main.lss
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10013c: e3a02c01 mov r2, #256 ; 0x100 100140: e3e030ff mvn r3, #255 ; 0xff 100144: e5832060 str r2, [r3, #96]
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
100148: e2822c7f add r2, r2, #32512 ; 0x7f00 10014c: e2433d07 sub r3, r3, #448 ; 0x1c0 100150: e5832004 str r2, [r3, #4]
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSecond
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
//// mt pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) ) | AT91C_CKGR_MOSCEN );
100154: e59f20a8 ldr r2, [pc, #168] ; 100204 <.text+0x204> 100158: e2433d05 sub r3, r3, #320 ; 0x140 10015c: e5832020 str r2, [r3, #32] // Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
100160: e59f20a0 ldr r2, [pc, #160] ; 100208 <.text+0x208> 100164: e5923068 ldr r3, [r2, #104] 100168: e3130001 tst r3, #1 ; 0x1 10016c: 0afffffb beq 100160 <AT91F_LowLevelInit+0x24> // 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 14 Fin = 1.3165 =(18,432 / 14)
// - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
// for 96 MHz the erroe is 0.11%
// Field out NOT USED = 0
// PLLCOUNT pll startup time estimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14 ) |
100170: e59f3094 ldr r3, [pc, #148] ; 10020c <.text+0x20c> 100174: e582302c str r3, [r2, #44] (AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (72<<16)));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
100178: e59f3088 ldr r3, [pc, #136] ; 100208 <.text+0x208> 10017c: e5933068 ldr r3, [r3, #104] 100180: e3130004 tst r3, #4 ; 0x4 100184: 0afffffb beq 100178 <AT91F_LowLevelInit+0x3c> while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
100188: e59f2078 ldr r2, [pc, #120] ; 100208 <.text+0x208> 10018c: e5923068 ldr r3, [r2, #104] 100190: e3130008 tst r3, #8 ; 0x8 100194: 0afffffb beq 100188 <AT91F_LowLevelInit+0x4c> // 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
100198: e3a03004 mov r3, #4 ; 0x4 10019c: e5823030 str r3, [r2, #48] while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
1001a0: e59f2060 ldr r2, [pc, #96] ; 100208 <.text+0x208> 1001a4: e5923068 ldr r3, [r2, #104] 1001a8: e3130008 tst r3, #8 ; 0x8 1001ac: 0afffffb beq 1001a0 <AT91F_LowLevelInit+0x64>
pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
1001b0: e5923030 ldr r3, [r2, #48] 1001b4: e3833003 orr r3, r3, #3 ; 0x3 1001b8: e5823030 str r3, [r2, #48] while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
1001bc: e59f3044 ldr r3, [pc, #68] ; 100208 <.text+0x208> 1001c0: e5933068 ldr r3, [r3, #104] 1001c4: e3130008 tst r3, #8 ; 0x8 1001c8: 0afffffb beq 1001bc <AT91F_LowLevelInit+0x80>
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
1001cc: e59f203c ldr r2, [pc, #60] ; 100210 <.text+0x210> 1001d0: e59f303c ldr r3, [pc, #60] ; 100214 <.text+0x214> 1001d4: e5832080 str r2, [r3, #128] 1001d8: e3a01001 mov r1, #1 ; 0x1 for (i=1;i < 31; i++)
{
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
1001dc: e1a02101 mov r2, r1, lsl #2 1001e0: e59f3030 ldr r3, [pc, #48] ; 100218 <.text+0x218> 1001e4: e2811001 add r1, r1, #1 ; 0x1 1001e8: e351001f cmp r1, #31 ; 0x1f 1001ec: e5023f80 str r3, [r2, #-3968] 1001f0: 1afffff9 bne 1001dc <AT91F_LowLevelInit+0xa0> }
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
1001f4: e59f2020 ldr r2, [pc, #32] ; 10021c <.text+0x21c> 1001f8: e59f3014 ldr r3, [pc, #20] ; 100214 <.text+0x214> 1001fc: e5832134 str r2, [r3, #308]
}
100200: e12fff1e bx lr 100204: 00000601 andeq r0, r0, r1, lsl #12 100208: fffffc00 swinv 0x00fffc00 10020c: 00481c0e subeq r1, r8, lr, lsl #24 100210: 0010010c andeqs r0, r0, ip, lsl #2 100214: fffff000 swinv 0x00fff000 100218: 00100110 andeqs r0, r0, r0, lsl r1 10021c: 00100114 andeqs r0, r0, r4, lsl r100100220 <Delay>:#define LCD_RESET_LOW m_pPioA->PIO_CODR = BIT2
#define LCD_RESET_HIGH m_pPioA->PIO_SODR = BIT2
//it's a simple delay
void Delay (unsigned long a) { while (--a!=0); }
100220: 2300 mov r3, #0 100222: 3301 add r3, #1 100224: 4283 cmp r3, r0 100226: d1fc bne 100222 <Delay+0x2> 100228: 4770 bx lr ...0010022c <main>:
extern char mmc_buffer[512];
unsigned char ch1 = 0x0;
unsigned char ch2 = 0x0;
char mmc_buffer_test_1[512];
char mmc_buffer_test_2[512];
char state_mmc = 1;
// loop variable
unsigned int i;
int main()
{
10022c: b5f0 push {r4, r5, r6, r7, lr}
// Freq init
InitFrec();
// Init periphery
InitPeriphery();
//AT91C_BASE_PMC->PMC_PCER = ( 1 << AT91C_ID_PIOA ) | ( 1 << AT91C_ID_PIOB ) | ( 1 << AT91C_ID_US0 );
//AT91C_BASE_PMC->PMC_PCER = ( 1 << AT91C_ID_US0 );
//uart0_init();
//uart0_puts("\n\nHI! INIT...OK\n");
AT91C_BASE_PIOB->PIO_OER = (AT91B_LCD_BL); // set to output
10022e: 4f2e ldr r7, [pc, #184] (1002e8 <.text+0x2e8>) 100230: 2680 mov r6, #128 100232: 0376 lsl r6, r6, #13 100234: fb04f000 bl 100840 <InitFrec> 100238: fb32f000 bl 1008a0 <InitPeriphery> 10023c: 613e str r6, [r7, #16] AT91C_BASE_PIOB->PIO_PER = (AT91B_LCD_BL); // set to PIO mode
10023e: 603e str r6, [r7, #0] AT91C_BASE_PIOB->PIO_PPUDR = (AT91B_LCD_BL); // disable pull up
100240: 663e str r6, [r7, #96]
/**** MMC CARD ****/
if (initMMC() == MMC_SUCCESS) // card found
100242: f9ebf000 bl 10061c <initMMC> 100246: 1c05 mov r5, r0 (add r5, r0, #0) 100248: 2800 cmp r0, #0 10024a: d14c bne 1002e6 <main+0xba> {
//card_state |= 1;
memset(&mmc_buffer,0,512);
10024c: 4c27 ldr r4, [pc, #156] (1002ec <.text+0x2ec>) 10024e: 2280 mov r2, #128 100250: 0092 lsl r2, r2, #2 100252: 2100 mov r1, #0 100254: 1c20 mov r0, r4 (add r0, r4, #0) 100256: fb53f000 bl 100900 <memset> mmcReadRegister (10, 16);
10025a: 2110 mov r1, #16 10025c: 200a mov r0, #10 10025e: fab1f000 bl 1007c4 <mmcReadRegister> mmc_buffer[7]=0;
// Fill first Block (0) with 'A'
memset(&mmc_buffer,'0',512); //set breakpoint and trace mmc_buffer contents
100262: 2280 mov r2, #128 100264: 2130 mov r1, #48 100266: 0092 lsl r2, r2, #2 100268: 71e5 strb r5, [r4, #7] 10026a: 1c20 mov r0, r4 (add r0, r4, #0) 10026c: fb48f000 bl 100900 <memset> mmcWriteBlock(0);
100270: 2000 mov r0, #0 100272: fa6df000 bl 100750 <mmcWriteBlock> // Fill second Block (1)-AbsAddr 512 with 'B'
memset(&mmc_buffer,'1',512);
100276: 2280 mov r2, #128 100278: 2131 mov r1, #49 10027a: 0092 lsl r2, r2, #2 10027c: 1c20 mov r0, r4 (add r0, r4, #0) 10027e: fb3ff000 bl 100900 <memset> mmcWriteBlock(512);
100282: 2080 mov r0, #128 100284: 0080 lsl r0, r0, #2 100286: fa63f000 bl 100750 <mmcWriteBlock>
// Read first Block back to buffer
memset(&mmc_buffer,0x00,512);
10028a: 2280 mov r2, #128 10028c: 0092 lsl r2, r2, #2 10028e: 2100 mov r1, #0 100290: 1c20 mov r0, r4 (add r0, r4, #0) 100292: fb35f000 bl 100900 <memset> mmcReadBlock(0,512);
100296: 2180 mov r1, #128 100298: 0089 lsl r1, r1, #2 10029a: 2000 mov r0, #0 10029c: fa22f000 bl 1006e4 <mmcReadBlock> if(strncmp(&mmc_buffer[0], &mmc_buffer_test_1[0], 512)) AT91C_BASE_PIOB->PIO_SODR = AT91B_LCD_BL;;
1002a0: 2280 mov r2, #128 1002a2: 4913 ldr r1, [pc, #76] (1002f0 <.text+0x2f0>) 1002a4: 1c20 mov r0, r4 (add r0, r4, #0) 1002a6: 0092 lsl r2, r2, #2 1002a8: fb5ef000 bl 100968 <strncmp> 1002ac: 2800 cmp r0, #0 1002ae: d000 beq 1002b2 <main+0x86> 1002b0: 633e str r6, [r7, #48]
// Read first Block back to buffer
memset(&mmc_buffer,0x00,512);
1002b2: 2280 mov r2, #128 1002b4: 0092 lsl r2, r2, #2 1002b6: 2100 mov r1, #0 1002b8: 1c20 mov r0, r4 (add r0, r4, #0) 1002ba: fb21f000 bl 100900 <memset> mmcReadBlock(512,512);
1002be: 2080 mov r0, #128 1002c0: 0080 lsl r0, r0, #2 1002c2: 1c01 mov r1, r0 (add r1, r0, #0) 1002c4: fa0ef000 bl 1006e4 <mmcReadBlock> if(strncmp(&mmc_buffer[0], &mmc_buffer_test_2[0], 512)) AT91C_BASE_PIOB->PIO_SODR = AT91B_LCD_BL;;
1002c8: 2280 mov r2, #128 1002ca: 490a ldr r1, [pc, #40] (1002f4 <.text+0x2f4>) 1002cc: 1c20 mov r0, r4 (add r0, r4, #0) 1002ce: 0092 lsl r2, r2, #2 1002d0: fb4af000 bl 100968 <strncmp> 1002d4: 2800 cmp r0, #0 1002d6: d000 beq 1002da <main+0xae> 1002d8: 633e str r6, [r7, #48]
memset(&mmc_buffer,0x00,512);
1002da: 2280 mov r2, #128 1002dc: 1c20 mov r0, r4 (add r0, r4, #0) 1002de: 2100 mov r1, #0 1002e0: 0092 lsl r2, r2, #2 1002e2: fb0df000 bl 100900 <memset> 1002e6: e7fe b 1002e6 <main+0xba> 1002e8: fffff600 bl fff012ea <Top_Stack+0xffcf12ea> 1002ec: 0066 lsl r6, r4, #1 1002ee: 0020 lsl r0, r4, #0 1002f0: 0268 lsl r0, r5, #9 1002f2: 0020 lsl r0, r4, #0 1002f4: 046c lsl r4, r5, #17 1002f6: 0020 lsl r0, r4, #0001002f8 <uart0_kbhit>:
int uart0_kbhit( void ) /* returns true if character in receive buffer */
{
if ( pUSART->US_CSR & AT91C_US_RXRDY) {
1002f8: 4b02 ldr r3, [pc, #8] (100304 <.text+0x304>) 1002fa: 681b ldr r3, [r3, #0] 1002fc: 6958 ldr r0, [r3, #20] 1002fe: 2301 mov r3, #1 100300: 4018 and r0, r3 return 1;
}
else {
return 0;
}
}
100302: 4770 bx lr 100304: 002c lsl r4, r5, #0 100306: 0020 lsl r0, r4, #000100308 <uart0_init>:
void uart0_init (void) { /* Initialize Serial Interface */
/* mt: n.b: uart0 clock must be enabled to use it */
*AT91C_PIOA_PDR = AT91C_PA0_RXD0 | /* Enable RxD0 Pin */
100308: 4b07 ldr r3, [pc, #28] (100328 <.text+0x328>) 10030a: 2203 mov r2, #3 10030c: 601a str r2, [r3, #0] AT91C_PA1_TXD0; /* Enalbe TxD0 Pin */
pUSART->US_CR = AT91C_US_RSTRX | /* Reset Receiver */
10030e: 4b07 ldr r3, [pc, #28] (10032c <.text+0x32c>) 100310: 681a ldr r2, [r3, #0] 100312: 23ac mov r3, #172 100314: 6013 str r3, [r2, #0] AT91C_US_RSTTX | /* Reset Transmitter */
AT91C_US_RXDIS | /* Receiver Disable */
AT91C_US_TXDIS; /* Transmitter Disable */
pUSART->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */
100316: 238c mov r3, #140 100318: 011b lsl r3, r3, #4 10031a: 6053 str r3, [r2, #4] AT91C_US_CLKS_CLOCK | /* Clock = MCK */
AT91C_US_CHRL_8_BITS | /* 8-bit Data */
AT91C_US_PAR_NONE | /* No Parity */
AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */
pUSART->US_BRGR = BRD; /* Baud Rate Divisor */
10031c: 231a mov r3, #26 10031e: 6213 str r3, [r2, #32]
pUSART->US_CR = AT91C_US_RXEN | /* Receiver Enable */
100320: 2350 mov r3, #80 100322: 6013 str r3, [r2, #0] AT91C_US_TXEN; /* Transmitter Enable */
}
100324: 4770 bx lr 100326: 0000 lsl r0, r0, #0 100328: fffff404 bl ffd0532a <Top_Stack+0xffaf532a> 10032c: 002c lsl r4, r5, #0 10032e: 0020 lsl r0, r4, #000100330 <uart0_putc>:
int uart0_putc(int ch)
{
while (!(pUSART->US_CSR & AT91C_US_TXRDY)); /* Wait for Empty Tx Buffer */
100330: 4b03 ldr r3, [pc, #12] (100340 <.text+0x340>) 100332: 681a ldr r2, [r3, #0] 100334: 6953 ldr r3, [r2, #20] 100336: 0799 lsl r1, r3, #30 100338: d5fc bpl 100334 <uart0_putc+0x4> return (pUSART->US_THR = ch); /* Transmit Character */
10033a: 61d0 str r0, [r2, #28] 10033c: 69d0 ldr r0, [r2, #28]}
10033e: 4770 bx lr 100340: 002c lsl r4, r5, #0 100342: 0020 lsl r0, r4, #000100344 <uart0_putchar>:
int uart0_putchar (int ch) { /* Write Character to Serial Port */
100344: b510 push {r4, lr} 100346: 1c04 mov r4, r0 (add r4, r0, #0)
if (ch == '\n') { /* Check for LF */
100348: 280a cmp r0, #10 10034a: d102 bne 100352 <uart0_putchar+0xe> uart0_putc( '\r' ); /* Output CR */
10034c: 200d mov r0, #13 10034e: ffeff7ff bl 100330 <uart0_putc> }
return uart0_putc( ch ); /* Transmit Character */
100352: 1c20 mov r0, r4 (add r0, r4, #0) 100354: ffecf7ff bl 100330 <uart0_putc>}
100358: bc10 pop {r4} 10035a: bc02 pop {r1} 10035c: 4708 bx r1 ...00100360 <uart0_puts>:
int uart0_puts ( char* s ){
100360: b510 push {r4, lr} 100362: 1c04 mov r4, r0 (add r4, r0, #0) 100364: e002 b 10036c <uart0_puts+0xc> while ( *s ) uart0_putchar( *s++ );
100366: 3401 add r4, #1 100368: ffecf7ff bl 100344 <uart0_putchar> 10036c: 7820 ldrb r0, [r4, #0] 10036e: 2800 cmp r0, #0 100370: d1f9 bne 100366 <uart0_puts+0x6> return 0;
}
100372: bc10 pop {r4} 100374: bc02 pop {r1} 100376: 4708 bx r100100378 <uart0_getc>:
int uart0_getc ( void ) /* Read Character from Serial Port */
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