📄 main.lss
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str r14, [r14, #AIC_EOICR]
1000f8: e58ee130 str lr, [lr, #304]
/*- Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r0}
1000fc: e8bd0001 ldmia sp!, {r0}
/*- Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r14}
100100: e8bd4000 ldmia sp!, {lr} msr SPSR_cxsf, r14
100104: e16ff00e msr SPSR_fsxc, lr
/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
ldmia sp!, {pc}^
100108: e8fd8000 ldmia sp!, {pc}^0010010c <AT91F_Default_FIQ_handler>:
.size IRQ_Handler_Entry, . - IRQ_Handler_Entry
.endfunc
/*---------------------------------------------------------------
//* ?EXEPTION_VECTOR
//* This module is only linked if needed for closing files.
//*---------------------------------------------------------------*/
.global AT91F_Default_FIQ_handler
.func AT91F_Default_FIQ_handler
AT91F_Default_FIQ_handler:
b AT91F_Default_FIQ_handler
10010c: eafffffe b 10010c <AT91F_Default_FIQ_handler>00100110 <AT91F_Default_IRQ_handler>: .size AT91F_Default_FIQ_handler, . - AT91F_Default_FIQ_handler
.endfunc
.global AT91F_Default_IRQ_handler
.func AT91F_Default_IRQ_handler
AT91F_Default_IRQ_handler:
b AT91F_Default_IRQ_handler
100110: eafffffe b 100110 <AT91F_Default_IRQ_handler>00100114 <AT91F_Spurious_handler>: .size AT91F_Default_IRQ_handler, . - AT91F_Default_IRQ_handler
.endfunc
.global AT91F_Spurious_handler
.func AT91F_Spurious_handler
AT91F_Spurious_handler:
b AT91F_Spurious_handler
100114: eafffffe b 100114 <AT91F_Spurious_handler> 100118: 0010013c andeqs r0, r0, ip, lsr r1 10011c: fffff000 swinv 0x00fff000 100120: 00100904 andeqs r0, r0, r4, lsl #18 100124: 00200000 eoreq r0, r0, r0 100128: 00200000 eoreq r0, r0, r0 10012c: 00200000 eoreq r0, r0, r0 100130: 00200000 eoreq r0, r0, r0 100134: 001000b8 ldreqh r0, [r0], -r8 100138: 00100359 andeqs r0, r0, r9, asr r30010013c <AT91F_LowLevelInit>://* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void)
{
10013c: e1a0c00d mov ip, sp 100140: e92dd800 stmdb sp!, {fp, ip, lr, pc} 100144: e24cb004 sub fp, ip, #4 ; 0x4 100148: e24dd008 sub sp, sp, #8 ; 0x8 int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
10014c: e3a03102 mov r3, #-2147483648 ; 0x80000000 100150: e1a03ac3 mov r3, r3, asr #21 100154: e50b3010 str r3, [fp, #-16] //* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
100158: e3e020ff mvn r2, #255 ; 0xff 10015c: e3a03c01 mov r3, #256 ; 0x100 100160: e5823060 str r3, [r2, #96]
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSecond
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
//// mt pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) ) | AT91C_CKGR_MOSCEN );
100164: e51b2010 ldr r2, [fp, #-16] 100168: e3a03c06 mov r3, #1536 ; 0x600 10016c: e2833001 add r3, r3, #1 ; 0x1 100170: e5823020 str r3, [r2, #32] // Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
100174: e51b3010 ldr r3, [fp, #-16] 100178: e5933068 ldr r3, [r3, #104] 10017c: e2033001 and r3, r3, #1 ; 0x1 100180: e3530000 cmp r3, #0 ; 0x0 100184: 0afffffa beq 100174 <AT91F_LowLevelInit+0x38> // 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 14 Fin = 1.3165 =(18,432 / 14)
// - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
// for 96 MHz the erroe is 0.11%
// Field out NOT USED = 0
// PLLCOUNT pll startup time estimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14 ) |
100188: e51b2010 ldr r2, [fp, #-16] 10018c: e3a03712 mov r3, #4718592 ; 0x480000 100190: e2833b07 add r3, r3, #7168 ; 0x1c00 100194: e283300e add r3, r3, #14 ; 0xe 100198: e582302c str r3, [r2, #44] (AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (72<<16)));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
10019c: e51b3010 ldr r3, [fp, #-16] 1001a0: e5933068 ldr r3, [r3, #104] 1001a4: e1a03123 mov r3, r3, lsr #2 1001a8: e2033001 and r3, r3, #1 ; 0x1 1001ac: e3530000 cmp r3, #0 ; 0x0 1001b0: 0afffff9 beq 10019c <AT91F_LowLevelInit+0x60> while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
1001b4: e51b3010 ldr r3, [fp, #-16] 1001b8: e5933068 ldr r3, [r3, #104] 1001bc: e1a031a3 mov r3, r3, lsr #3 1001c0: e2033001 and r3, r3, #1 ; 0x1 1001c4: e3530000 cmp r3, #0 ; 0x0 1001c8: 0afffff9 beq 1001b4 <AT91F_LowLevelInit+0x78> // 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
1001cc: e51b2010 ldr r2, [fp, #-16] 1001d0: e3a03004 mov r3, #4 ; 0x4 1001d4: e5823030 str r3, [r2, #48] while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
1001d8: e51b3010 ldr r3, [fp, #-16] 1001dc: e5933068 ldr r3, [r3, #104] 1001e0: e1a031a3 mov r3, r3, lsr #3 1001e4: e2033001 and r3, r3, #1 ; 0x1 1001e8: e3530000 cmp r3, #0 ; 0x0 1001ec: 0afffff9 beq 1001d8 <AT91F_LowLevelInit+0x9c>
pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
1001f0: e51b3010 ldr r3, [fp, #-16] 1001f4: e5933030 ldr r3, [r3, #48] 1001f8: e3832003 orr r2, r3, #3 ; 0x3 1001fc: e51b3010 ldr r3, [fp, #-16] 100200: e5832030 str r2, [r3, #48] while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
100204: e51b3010 ldr r3, [fp, #-16] 100208: e5933068 ldr r3, [r3, #104] 10020c: e1a031a3 mov r3, r3, lsr #3 100210: e2033001 and r3, r3, #1 ; 0x1 100214: e3530000 cmp r3, #0 ; 0x0 100218: 0afffff9 beq 100204 <AT91F_LowLevelInit+0xc8>
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
10021c: e3a03102 mov r3, #-2147483648 ; 0x80000000 100220: e1a039c3 mov r3, r3, asr #19 100224: e59f2068 ldr r2, [pc, #104] ; 100294 <.text+0x294> 100228: e5832080 str r2, [r3, #128] for (i=1;i < 31; i++)
10022c: e3a03001 mov r3, #1 ; 0x1 100230: e50b3014 str r3, [fp, #-20] 100234: ea00000c b 10026c <AT91F_LowLevelInit+0x130> {
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
100238: e3a02102 mov r2, #-2147483648 ; 0x80000000 10023c: e1a029c2 mov r2, r2, asr #19 100240: e51b0014 ldr r0, [fp, #-20] 100244: e59f304c ldr r3, [pc, #76] ; 100298 <.text+0x298> 100248: e1a0c003 mov ip, r3 10024c: e3a01080 mov r1, #128 ; 0x80 100250: e1a03100 mov r3, r0, lsl #2 100254: e0833002 add r3, r3, r2 100258: e0833001 add r3, r3, r1 10025c: e583c000 str ip, [r3] 100260: e51b3014 ldr r3, [fp, #-20] 100264: e2833001 add r3, r3, #1 ; 0x1 100268: e50b3014 str r3, [fp, #-20] 10026c: e51b3014 ldr r3, [fp, #-20] 100270: e353001e cmp r3, #30 ; 0x1e 100274: daffffef ble 100238 <AT91F_LowLevelInit+0xfc> }
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
100278: e3a03102 mov r3, #-2147483648 ; 0x80000000 10027c: e1a039c3 mov r3, r3, asr #19 100280: e59f2014 ldr r2, [pc, #20] ; 10029c <.text+0x29c> 100284: e5832134 str r2, [r3, #308]
}
100288: e24bd00c sub sp, fp, #12 ; 0xc 10028c: e89d6800 ldmia sp, {fp, sp, lr} 100290: e12fff1e bx lr 100294: 0010010c andeqs r0, r0, ip, lsl #2 100298: 00100110 andeqs r0, r0, r0, lsl r1 10029c: 00100114 andeqs r0, r0, r4, lsl r1001002a0 <Delay>:#include "include/include.h"
void Delay (unsigned long var){
1002a0: b580 push {r7, lr} 1002a2: 466f mov r7, sp 1002a4: b081 sub sp, #4 1002a6: 1f3b sub r3, r7, #4 1002a8: 6018 str r0, [r3, #0] while(--var != 0) ;
1002aa: 1f3a sub r2, r7, #4 1002ac: 1f3b sub r3, r7, #4 1002ae: 681b ldr r3, [r3, #0] 1002b0: 3b01 sub r3, #1 1002b2: 6013 str r3, [r2, #0] 1002b4: 1f3b sub r3, r7, #4 1002b6: 681b ldr r3, [r3, #0] 1002b8: 2b00 cmp r3, #0 1002ba: d1f6 bne 1002aa <Delay+0xa>}
1002bc: 46bd mov sp, r7 1002be: bc80 pop {r7} 1002c0: bc01 pop {r0} 1002c2: 4700 bx r0001002c4 <ConfigureIO>:
/*-----------------------------------------------------------------------------
*-----------------------------------------------------------------------------*/
static void ConfigureIO (void){
1002c4: b580 push {r7, lr} 1002c6: 466f mov r7, sp // for LCD Backlight
AT91C_BASE_PIOB->PIO_OER = (AUDIO_OUT); // set to output
1002c8: 4a10 ldr r2, [pc, #64] (10030c <.text+0x30c>) 1002ca: 2380 mov r3, #128 1002cc: 031b lsl r3, r3, #12 1002ce: 6113 str r3, [r2, #16] AT91C_BASE_PIOB->PIO_PER = (AUDIO_OUT); // set to PIO mode
1002d0: 4a0e ldr r2, [pc, #56] (10030c <.text+0x30c>) 1002d2: 2380 mov r3, #128 1002d4: 031b lsl r3, r3, #12 1002d6: 6013 str r3, [r2, #0]
AT91C_BASE_PIOB->PIO_OER = (USB_PULLUP); // set to output
1002d8: 4a0c ldr r2, [pc, #48] (10030c <.text+0x30c>) 1002da: 2380 mov r3, #128 1002dc: 049b lsl r3, r3, #18 1002de: 6113 str r3, [r2, #16] AT91C_BASE_PIOB->PIO_PER = (USB_PULLUP); // set to PIO mode
1002e0: 4a0a ldr r2, [pc, #40] (10030c <.text+0x30c>) 1002e2: 2380 mov r3, #128 1002e4: 049b lsl r3, r3, #18 1002e6: 6013 str r3, [r2, #0]
AT91C_BASE_PIOB->PIO_PPUDR = (AUDIO_OUT); // disable pull up
1002e8: 4a08 ldr r2, [pc, #32] (10030c <.text+0x30c>) 1002ea: 2380 mov r3, #128 1002ec: 031b lsl r3, r3, #12 1002ee: 6613 str r3, [r2, #96] AT91C_BASE_PIOB->PIO_PPUDR = (USB_PULLUP); // disable pin pull up
1002f0: 4a06 ldr r2, [pc, #24] (10030c <.text+0x30c>) 1002f2: 2380 mov r3, #128 1002f4: 049b lsl r3, r3, #18 1002f6: 6613 str r3, [r2, #96]
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PIOA); // enable periph clock for PIO controller
1002f8: 4a05 ldr r2, [pc, #20] (100310 <.text+0x310>) 1002fa: 2304 mov r3, #4 1002fc: 6113 str r3, [r2, #16] AT91C_BASE_PIOA->PIO_ODR = (AT91A_JS_ALL); // set PIO line to input
1002fe: 4a05 ldr r2, [pc, #20] (100314 <.text+0x314>) 100300: 4b05 ldr r3, [pc, #20] (100318 <.text+0x318>) 100302: 6153 str r3, [r2, #20]}
100304: 46bd mov sp, r7 100306: bc80 pop {r7} 100308: bc01 pop {r0} 10030a: 4700 bx r0 10030c: fffff600 bl fff0130e <Top_Stack+0xffcf130e> 100310: fc00 second half of BL instruction 0xfc00 100312: ffff second half of BL instruction 0xffff 100314: fffff400 bl ffd01316 <Top_Stack+0xffaf1316> 100318: c380 stmia r3!,{r7} ...0010031c <WD_reset>:
//Reset WatchDog to avoid MC restsrt
void WD_reset(void){
10031c: b580 push {r7, lr} 10031e: 466f mov r7, sp AT91C_BASE_WDTC->WDTC_WDCR = 0xA5000001;
100320: 4a03 ldr r2, [pc, #12] (100330 <.text+0x330>) 100322: 4b04 ldr r3, [pc, #16] (100334 <.text+0x334>) 100324: 6013 str r3, [r2, #0]}
100326: 46bd mov sp, r7 100328: bc80 pop {r7} 10032a: bc01 pop {r0} 10032c: 4700 bx r0 10032e: 0000 lsl r0, r0, #0 100330: fd40 second half of BL instruction 0xfd40 100332: ffff second half of BL instruction 0xffff 100334: 0001 lsl r1, r0, #0 100336: a500 add r5, pc, #0 (adr r5,100338 <Watchdog_set>)00100338 <Watchdog_set>:
//Configures Watchdog
//If ms_time < 4 or > 16 000 ms then watchdog is disabled
void Watchdog_set(unsigned int ms){
100338: b580 push {r7, lr} 10033a: 466f mov r7, sp 10033c: b081 sub sp, #4 10033e: 1f3b sub r3, r7, #4 100340: 6018 str r0, [r3, #0] //软桷栲腓玎鲨⌨️ 快捷键说明
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