ahbahb.vhd

AMBA总线AHB TO AHB bridge

----------------------------------------------------------------------------
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.
--
-----------------------------------------------------------------------------   
-- Entity:      ahbahb
-- File:        ahbahb.vhd
-- Author:      MobileUne	
-- Description: AMBA AHB-AHB Bridge (Multiple Slave to Master)
------------------------------------------------------------------------------ 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.amba.all;

entity ahbahb is
  generic (
    slaves : integer := 2
  );
  port (
    resetn  : in  std_logic;
    clk     : in  std_logic;
    slvi    : in  ahb_slv_in_vector(slaves-1 downto 0);
    slvo    : out ahb_slv_out_vector(slaves-1 downto 0);
    msti    : in  ahb_mst_in_type;
    msto    : out ahb_mst_out_type
  );
end;

architecture rtl of ahbahb is

type reg_type is record
  slvi : ahb_slv_in_vector(slaves-1 downto 0);
  slvo : ahb_slv_out_type;
  msti : ahb_mst_in_type;
  msto : ahb_mst_out_type;
  busgrant : std_logic;
  control : std_logic;
  ready : std_logic;
end record;

signal r, rin : reg_type;


begin

  comb : process(resetn, msti, slvi, r)
  variable rv : reg_type;
  variable sl_master : integer;
  variable sl_muxctrl : integer;
  variable slvgrant : std_logic_vector(slaves-1 downto 0);
  variable htrans : std_logic_vector(1 downto 0);

  begin

    if resetn/='1' then sl_master:=slaves; end if;

-- Slave select arbitration
    if (msti.hgrant='0') or (r.ready='1') then
      if ((sl_master/=slaves) and (r.slvi(sl_master).hsel and r.slvi(sl_master).hready)='0') or sl_master=slaves then
        sl_master := slaves;
        for i in 0 to slaves-1 loop
          if r.slvi(i).hsel='1' and r.slvi(i).hready='1' then
            sl_master := i;
          end if;
        end loop;
      end if;
    end if;

    if (msti.hgrant and msti.hready)='1' then
      rv.busgrant := '1';
    --elsif r.msti.hgrant='0' then
    elsif msti.hgrant='0' then
      rv.busgrant := '0';
    else 
      rv.busgrant := r.busgrant;
    end if;

    if r.ready='1' then
      rv.control := '0'; 
    elsif (rv.msto.hbusreq and msti.hgrant and msti.hready and r.busgrant)='1' then
      rv.control := '1';
    -- elsif msti.hgrant='0' then
    --  rv.control := '0';
    else 
      rv.control := r.control;
    end if;
      
    if (rv.msto.hbusreq and msti.hgrant and msti.hready and r.control)='1' then
      rv.ready := '1';
    else 
      rv.ready := '0';
    end if;
      
-- Slave access grant control mux
    for i in 0 to slaves-1 loop
      if i=sl_master then
        slvgrant(i) := rv.control;
      else
        slvgrant(i) := '0';
      end if;
    end loop;

-- Latch all input AHB slave signals
    for i in 0 to slaves-1 loop
      if (slvi(i).hsel = '1' and slvi(i).hready='1') or (slvgrant(i)='1') then
        rv.slvi(i) := slvi(i);
      else
        rv.slvi(i) := r.slvi(i);
      end if;
    end loop;

-- Bus request
    if sl_master/=slaves then
      rv.msto.hbusreq:='1';
    else
      rv.msto.hbusreq:='0';
    end if;

-- input ahb slave bus mux
    if sl_master/=slaves then
      sl_muxctrl:=sl_master;
    else 
      sl_muxctrl:=0;
    end if;
    
    msto.hbusreq <= r.msto.hbusreq;
    if r.msto.hbusreq='1' then
      htrans := r.slvi(sl_muxctrl).htrans;
      msto.hlock <= '1';
    else
      htrans := "00";
      msto.hlock <= '0';
    end if;
    msto.htrans <= htrans;
    -- msto.htrans <= r.slvi(sl_muxctrl).htrans;
    msto.haddr <= r.slvi(sl_muxctrl).haddr;
    msto.hwrite <= r.slvi(sl_muxctrl).hwrite;
    msto.hsize <= r.slvi(sl_muxctrl).hsize;
    msto.hburst <= r.slvi(sl_muxctrl).hburst;
    msto.hprot <= r.slvi(sl_muxctrl).hprot;
    msto.hwdata <= r.slvi(sl_muxctrl).hwdata;

    rv.msti.hgrant := msti.hgrant;
    rv.msti.hready := msti.hready;
    rv.slvo.hready := rv.ready;
    rv.slvo.hresp := msti.hresp;
    rv.slvo.hrdata := msti.hrdata;
    rv.slvo.hsplit := (others=>'0');

-- output ahb slave bus mux
    for i in 0 to slaves-1 loop
      slvo(i).hresp <= rv.slvo.hresp;
      slvo(i).hrdata <= rv.slvo.hrdata;
      slvo(i).hsplit <= rv.slvo.hsplit;
      if i=sl_master then
        --slvo(i).hready <= r.slvo.hready;
        slvo(i).hready <= rv.slvo.hready;--direct out; timing might be critical
      else
        slvo(i).hready <= '0';
      end if;
    end loop;  
    
    rin <= rv;

  end process;

  reg0 : process(resetn,clk)
  begin if rising_edge(clk) then r <= rin; end if; end process;

end;