📄 mac.h
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//
// Bits in the IMR register
//
#define IMR_MEASURESTART 0x80000000 //
#define IMR_QUIETSTART 0x20000000 //
#define IMR_RADARDETECT 0x10000000 //
#define IMR_MEASUREEND 0x08000000 //
#define IMR_SOFTTIMER1 0x00200000 //
//#define IMR_SYNCFLUSHOK 0x00100000 //
//#define IMR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
//#define IMR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
//#define IMR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
//#define IMR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
//#define IMR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
//#define IMR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
//#define IMR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
#define IMR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
#define IMR_RXNOBUF 0x00000800 //
#define IMR_MIBNEARFULL 0x00000400 //
#define IMR_SOFTINT 0x00000200 //
#define IMR_FETALERR 0x00000100 //
#define IMR_WATCHDOG 0x00000080 //
#define IMR_SOFTTIMER 0x00000040 //
#define IMR_GPIO 0x00000020 //
#define IMR_TBTT 0x00000010 //
#define IMR_RXDMA0 0x00000008 //
#define IMR_BNTX 0x00000004 //
#define IMR_AC0DMA 0x00000002 //
#define IMR_TXDMA0 0x00000001 //
//
// Bits in the ISR register
//
#define ISR_MEASURESTART 0x80000000 //
#define ISR_QUIETSTART 0x20000000 //
#define ISR_RADARDETECT 0x10000000 //
#define ISR_MEASUREEND 0x08000000 //
#define ISR_SOFTTIMER1 0x00200000 //
//#define ISR_SYNCFLUSHOK 0x00100000 //0001 0000 0000 0000 0000 0000
//#define ISR_ATIMEND 0x00080000 //0000 1000 0000 0000 0000 0000
//#define ISR_CFPEND 0x00040000 //0000 0100 0000 0000 0000 0000
//#define ISR_AC3DMA 0x00020000 //0000 0010 0000 0000 0000 0000
//#define ISR_AC2DMA 0x00010000 //0000 0001 0000 0000 0000 0000
//#define ISR_AC1DMA 0x00008000 //0000 0000 1000 0000 0000 0000
//#define ISR_SYNCTX 0x00004000 //0000 0000 0100 0000 0000 0000
//#define ISR_ATIMTX 0x00002000 //0000 0000 0010 0000 0000 0000
#define ISR_RXDMA1 0x00001000 //0000 0000 0001 0000 0000 0000
#define ISR_RXNOBUF 0x00000800 //0000 0000 0000 1000 0000 0000
#define ISR_MIBNEARFULL 0x00000400 //0000 0000 0000 0100 0000 0000
#define ISR_SOFTINT 0x00000200 //
#define ISR_FETALERR 0x00000100 //
#define ISR_WATCHDOG 0x00000080 //
#define ISR_SOFTTIMER 0x00000040 //
#define ISR_GPIO 0x00000020 //
#define ISR_TBTT 0x00000010 //
#define ISR_RXDMA0 0x00000008 //
#define ISR_BNTX 0x00000004 //
#define ISR_AC0DMA 0x00000002 //
#define ISR_TXDMA0 0x00000001 //
//
// Bits in the PSCFG register
//
#define PSCFG_PHILIPMD 0x40 //
#define PSCFG_WAKECALEN 0x20 //
#define PSCFG_WAKETMREN 0x10 //
#define PSCFG_BBPSPROG 0x08 //
#define PSCFG_WAKESYN 0x04 //
#define PSCFG_SLEEPSYN 0x02 //
#define PSCFG_AUTOSLEEP 0x01 //
//
// Bits in the PSCTL register
//
#define PSCTL_WAKEDONE 0x20 //
#define PSCTL_PS 0x10 //
#define PSCTL_GO2DOZE 0x08 //
#define PSCTL_LNBCN 0x04 //
#define PSCTL_ALBCN 0x02 //
#define PSCTL_PSEN 0x01 //
//
// Bits in the PSPWSIG register
//
#define PSSIG_WPE3 0x80 //
#define PSSIG_WPE2 0x40 //
#define PSSIG_WPE1 0x20 //
#define PSSIG_WRADIOPE 0x10 //
#define PSSIG_SPE3 0x08 //
#define PSSIG_SPE2 0x04 //
#define PSSIG_SPE1 0x02 //
#define PSSIG_SRADIOPE 0x01 //
//
// Bits in the BBREGCTL register
//
#define BBREGCTL_DONE 0x04 //
#define BBREGCTL_REGR 0x02 //
#define BBREGCTL_REGW 0x01 //
//
// Bits in the IFREGCTL register
//
#define IFREGCTL_DONE 0x04 //
#define IFREGCTL_IFRF 0x02 //
#define IFREGCTL_REGW 0x01 //
//
// Bits in the SOFTPWRCTL register
//
#define SOFTPWRCTL_RFLEOPT 0x0800 //
#define SOFTPWRCTL_TXPEINV 0x0200 //
#define SOFTPWRCTL_SWPECTI 0x0100 //
#define SOFTPWRCTL_SWPAPE 0x0020 //
#define SOFTPWRCTL_SWCALEN 0x0010 //
#define SOFTPWRCTL_SWRADIO_PE 0x0008 //
#define SOFTPWRCTL_SWPE2 0x0004 //
#define SOFTPWRCTL_SWPE1 0x0002 //
#define SOFTPWRCTL_SWPE3 0x0001 //
//
// Bits in the GPIOCTL1 register
//
#define GPIO1_DATA1 0x20 //
#define GPIO1_MD1 0x10 //
#define GPIO1_DATA0 0x02 //
#define GPIO1_MD0 0x01 //
//
// Bits in the DMACTL register
//
#define DMACTL_CLRRUN 0x00080000 //
#define DMACTL_RUN 0x00000008 //
#define DMACTL_WAKE 0x00000004 //
#define DMACTL_DEAD 0x00000002 //
#define DMACTL_ACTIVE 0x00000001 //
//
// Bits in the RXDMACTL0 register
//
#define RX_PERPKT 0x00000100 //
#define RX_PERPKTCLR 0x01000000 //
//
// Bits in the BCNDMACTL register
//
#define BEACON_READY 0x01 //
//
// Bits in the MISCFFCTL register
//
#define MISCFFCTL_WRITE 0x0001 //
//
// Bits in WAKEUPEN0
//
#define WAKEUPEN0_DIRPKT 0x10
#define WAKEUPEN0_LINKOFF 0x08
#define WAKEUPEN0_ATIMEN 0x04
#define WAKEUPEN0_TIMEN 0x02
#define WAKEUPEN0_MAGICEN 0x01
//
// Bits in WAKEUPEN1
//
#define WAKEUPEN1_128_3 0x08
#define WAKEUPEN1_128_2 0x04
#define WAKEUPEN1_128_1 0x02
#define WAKEUPEN1_128_0 0x01
//
// Bits in WAKEUPSR0
//
#define WAKEUPSR0_DIRPKT 0x10
#define WAKEUPSR0_LINKOFF 0x08
#define WAKEUPSR0_ATIMEN 0x04
#define WAKEUPSR0_TIMEN 0x02
#define WAKEUPSR0_MAGICEN 0x01
//
// Bits in WAKEUPSR1
//
#define WAKEUPSR1_128_3 0x08
#define WAKEUPSR1_128_2 0x04
#define WAKEUPSR1_128_1 0x02
#define WAKEUPSR1_128_0 0x01
//
// Bits in the MAC_REG_GPIOCTL register
//
#define GPIO0_MD 0x01 //
#define GPIO0_DATA 0x02 //
#define GPIO0_INTMD 0x04 //
#define GPIO1_MD 0x10 //
#define GPIO1_DATA 0x20 //
//
// Bits in the MSRCTL register
//
#define MSRCTL_FINISH 0x80
#define MSRCTL_READY 0x40
#define MSRCTL_RADARDETECT 0x20
#define MSRCTL_EN 0x10
#define MSRCTL_QUIETTXCHK 0x08
#define MSRCTL_QUIETRPT 0x04
#define MSRCTL_QUIETINT 0x02
#define MSRCTL_QUIETEN 0x01
//
// Bits in the MSRCTL1 register
//
#define MSRCTL1_TXPWR 0x08
#define MSRCTL1_CSAPAREN 0x04
#define MSRCTL1_TXPAUSE 0x01
// Loopback mode
#define MAC_LB_EXT 0x02 //
#define MAC_LB_INTERNAL 0x01 //
#define MAC_LB_NONE 0x00 //
// Ethernet address filter type
#define PKT_TYPE_NONE 0x00 // turn off receiver
#define PKT_TYPE_ALL_MULTICAST 0x80
#define PKT_TYPE_PROMISCUOUS 0x40
#define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
#define PKT_TYPE_BROADCAST 0x10
#define PKT_TYPE_MULTICAST 0x08
#define PKT_TYPE_ERROR_WPA 0x04
#define PKT_TYPE_ERROR_CRC 0x02
#define PKT_TYPE_BSSID 0x01
#define Default_BI 0x200
// MiscFIFO Offset
#define MISCFIFO_KEYETRY0 32
#define MISCFIFO_KEYENTRYSIZE 22
#define MISCFIFO_SYNINFO_IDX 10
#define MISCFIFO_SYNDATA_IDX 11
#define MISCFIFO_SYNDATASIZE 21
// enabled mask value of irq
#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
IMR_RXDMA1 | \
IMR_RXNOBUF | \
IMR_MIBNEARFULL | \
IMR_SOFTINT | \
IMR_FETALERR | \
IMR_WATCHDOG | \
IMR_SOFTTIMER | \
IMR_GPIO | \
IMR_TBTT | \
IMR_RXDMA0 | \
IMR_BNTX | \
IMR_AC0DMA | \
IMR_TXDMA0)
// max time out delay time
#define W_MAX_TIMEOUT 0xFFF0U //
// wait time within loop
#define CB_DELAY_LOOP_WAIT 10 // 10ms
//
// revision id
//
#define REV_ID_VT3253_A0 0x00
#define REV_ID_VT3253_A1 0x01
#define REV_ID_VT3253_B0 0x08
#define REV_ID_VT3253_B1 0x09
/*--------------------- Export Types ------------------------------*/
/*--------------------- Export Macros ------------------------------*/
#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
{ \
BYTE byData; \
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
}
#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
{ \
WORD wData; \
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
}
#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
{ \
DWORD dwData; \
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
}
#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
{ \
BYTE byData; \
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
byData &= byMask; \
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
}
#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
{ \
BYTE byData; \
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
}
#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
{ \
WORD wData; \
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
}
#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
{ \
DWORD dwData; \
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
}
#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
(PDWORD)pdwCurrDescAddr); \
}
#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
(PDWORD)pdwCurrDescAddr); \
}
#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
(PDWORD)pdwCurrDescAddr); \
}
#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
(PDWORD)pdwCurrDescAddr); \
}
#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
(PDWORD)pdwCurrDescAddr); \
}
#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
{ \
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
(PDWORD)pdwCurrDescAddr); \
} \
// set the chip with current BCN tx descriptor address
#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
{ \
VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
dwCurrDescAddr); \
}
// set the chip with current BCN length
#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
{ \
VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
wCurrBCNLength); \
}
#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
{ \
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
(PBYTE)pbyEtherAddr); \
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
pbyEtherAddr + 1); \
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
pbyEtherAddr + 2); \
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