📄 mac.h
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/*
* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
* All rights reserved.
*
* This software is copyrighted by and is the sole property of
* VIA Networking Technologies, Inc. This software may only be used
* in accordance with the corresponding license agreement. Any unauthorized
* use, duplication, transmission, distribution, or disclosure of this
* software is expressly forbidden.
*
* This software is provided by VIA Networking Technologies, Inc. "as is"
* and any express or implied warranties, including, but not limited to, the
* implied warranties of merchantability and fitness for a particular purpose
* are disclaimed. In no event shall VIA Networking Technologies, Inc.
* be liable for any direct, indirect, incidental, special, exemplary, or
* consequential damages.
*
*
* File: mac.h
*
* Purpose: MAC routines
*
* Author: Tevin Chen
*
* Date: May 21, 1996
* Revision History:
* 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
* 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
* 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
*
*/
#ifndef __MAC_H__
#define __MAC_H__
#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif
#if !defined(__TMACRO_H__)
#include "tmacro.h"
#endif
#if !defined(__UPC_H__)
#include "upc.h"
#endif
/*--------------------- Export Definitions -------------------------*/
//
// Registers in the MAC
//
#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
#define MAC_MAX_CONTEXT_SIZE MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1
// Registers not related to 802.11b
#define MAC_REG_BCFG0 0x00
#define MAC_REG_BCFG1 0x01
#define MAC_REG_FCR0 0x02
#define MAC_REG_FCR1 0x03
#define MAC_REG_BISTCMD 0x04
#define MAC_REG_BISTSR0 0x05
#define MAC_REG_BISTSR1 0x06
#define MAC_REG_BISTSR2 0x07
#define MAC_REG_I2MCSR 0x08
#define MAC_REG_I2MTGID 0x09
#define MAC_REG_I2MTGAD 0x0A
#define MAC_REG_I2MCFG 0x0B
#define MAC_REG_I2MDIPT 0x0C
#define MAC_REG_I2MDOPT 0x0E
#define MAC_REG_PMC0 0x10
#define MAC_REG_PMC1 0x11
#define MAC_REG_STICKHW 0x12
#define MAC_REG_LOCALID 0x14
#define MAC_REG_TESTCFG 0x15
#define MAC_REG_JUMPER0 0x16
#define MAC_REG_JUMPER1 0x17
#define MAC_REG_TMCTL0 0x18
#define MAC_REG_TMCTL1 0x19
#define MAC_REG_TMDATA0 0x1C
// MAC Parameter related
#define MAC_REG_LRT 0x20 //
#define MAC_REG_SRT 0x21 //
#define MAC_REG_SIFS 0x22 //
#define MAC_REG_DIFS 0x23 //
#define MAC_REG_EIFS 0x24 //
#define MAC_REG_SLOT 0x25 //
#define MAC_REG_BI 0x26 //
#define MAC_REG_CWMAXMIN0 0x28 //
#define MAC_REG_LINKOFFTOTM 0x2A
#define MAC_REG_SWTMOT 0x2B
#define MAC_REG_MIBCNTR 0x2C
#define MAC_REG_RTSOKCNT 0x2C
#define MAC_REG_RTSFAILCNT 0x2D
#define MAC_REG_ACKFAILCNT 0x2E
#define MAC_REG_FCSERRCNT 0x2F
// TSF Related
#define MAC_REG_TSFCNTR 0x30 //
#define MAC_REG_NEXTTBTT 0x38 //
#define MAC_REG_TSFOFST 0x40 //
#define MAC_REG_TFTCTL 0x48 //
// WMAC Control/Status Related
#define MAC_REG_ENCFG 0x4C //
#define MAC_REG_PAGE1SEL 0x4F //
#define MAC_REG_CFG 0x50 //
#define MAC_REG_TEST 0x52 //
#define MAC_REG_HOSTCR 0x54 //
#define MAC_REG_MACCR 0x55 //
#define MAC_REG_RCR 0x56 //
#define MAC_REG_TCR 0x57 //
#define MAC_REG_IMR 0x58 //
#define MAC_REG_ISR 0x5C
// Power Saving Related
#define MAC_REG_PSCFG 0x60 //
#define MAC_REG_PSCTL 0x61 //
#define MAC_REG_PSPWRSIG 0x62 //
#define MAC_REG_BBCR13 0x63
#define MAC_REG_AIDATIM 0x64
#define MAC_REG_PWBT 0x66
#define MAC_REG_WAKEOKTMR 0x68
#define MAC_REG_CALTMR 0x69
#define MAC_REG_SYNSPACCNT 0x6A
#define MAC_REG_WAKSYNOPT 0x6B
// Baseband/IF Control Group
#define MAC_REG_BBREGCTL 0x6C //
#define MAC_REG_CHANNEL 0x6D
#define MAC_REG_BBREGADR 0x6E
#define MAC_REG_BBREGDATA 0x6F
#define MAC_REG_IFREGCTL 0x70 //
#define MAC_REG_IFDATA 0x71 //
#define MAC_REG_ITRTMSET 0x74 //
#define MAC_REG_PAPEDELAY 0x77 //
#define MAC_REG_SOFTPWRCTL 0x78 //
#define MAC_REG_GPIOCTL0 0x7A //
#define MAC_REG_GPIOCTL1 0x7B //
// MAC DMA Related Group
#define MAC_REG_TXDMACTL0 0x7C //
#define MAC_REG_TXDMAPTR0 0x80 //
#define MAC_REG_AC0DMACTL 0x84 //
#define MAC_REG_AC0DMAPTR 0x88 //
#define MAC_REG_BCNDMACTL 0x8C //
#define MAC_REG_BCNDMAPTR 0x90 //
#define MAC_REG_RXDMACTL0 0x94 //
#define MAC_REG_RXDMAPTR0 0x98 //
#define MAC_REG_RXDMACTL1 0x9C //
#define MAC_REG_RXDMAPTR1 0xA0 //
#define MAC_REG_SYNCDMACTL 0xA4 //
#define MAC_REG_SYNCDMAPTR 0xA8
#define MAC_REG_ATIMDMACTL 0xAC
#define MAC_REG_ATIMDMAPTR 0xB0
// MiscFF PIO related
#define MAC_REG_MISCFFNDEX 0xB4
#define MAC_REG_MISCFFCTL 0xB6
#define MAC_REG_MISCFFDATA 0xB8
// Extend SW Timer
#define MAC_REG_TMDATA1 0xBC
// WOW Related Group
#define MAC_REG_WAKEUPEN0 0xC0
#define MAC_REG_WAKEUPEN1 0xC1
#define MAC_REG_WAKEUPSR0 0xC2
#define MAC_REG_WAKEUPSR1 0xC3
#define MAC_REG_WAKE128_0 0xC4
#define MAC_REG_WAKE128_1 0xD4
#define MAC_REG_WAKE128_2 0xE4
#define MAC_REG_WAKE128_3 0xF4
/////////////// Page 1 ///////////////////
#define MAC_REG_CRC_128_0 0x04
#define MAC_REG_CRC_128_1 0x06
#define MAC_REG_CRC_128_2 0x08
#define MAC_REG_CRC_128_3 0x0A
// MAC Configuration Group
#define MAC_REG_PAR0 0x0C
#define MAC_REG_PAR4 0x10
#define MAC_REG_BSSID0 0x14
#define MAC_REG_BSSID4 0x18
#define MAC_REG_MAR0 0x1C
#define MAC_REG_MAR4 0x20
// MAC RSPPKT INFO Group
#define MAC_REG_RSPINF_B_1 0x24
#define MAC_REG_RSPINF_B_2 0x28
#define MAC_REG_RSPINF_B_5 0x2C
#define MAC_REG_RSPINF_B_11 0x30
#define MAC_REG_RSPINF_A_6 0x34
#define MAC_REG_RSPINF_A_9 0x36
#define MAC_REG_RSPINF_A_12 0x38
#define MAC_REG_RSPINF_A_18 0x3A
#define MAC_REG_RSPINF_A_24 0x3C
#define MAC_REG_RSPINF_A_36 0x3E
#define MAC_REG_RSPINF_A_48 0x40
#define MAC_REG_RSPINF_A_54 0x42
#define MAC_REG_RSPINF_A_72 0x44
// 802.11h relative
#define MAC_REG_QUIETINIT 0x60
#define MAC_REG_QUIETGAP 0x62
#define MAC_REG_QUIETDUR 0x64
#define MAC_REG_MSRCTL 0x66
#define MAC_REG_MSRBBSTS 0x67
#define MAC_REG_MSRSTART 0x68
#define MAC_REG_MSRDURATION 0x70
#define MAC_REG_CCAFRACTION 0x72
#define MAC_REG_PWRCCK 0x73
#define MAC_REG_PWROFDM 0x7C
//
// Bits in the BCFG0 register
//
#define BCFG0_PERROFF 0x40
#define BCFG0_MRDMDIS 0x20
#define BCFG0_MRDLDIS 0x10
#define BCFG0_MWMEN 0x08
#define BCFG0_VSERREN 0x02
#define BCFG0_LATMEN 0x01
//
// Bits in the BCFG1 register
//
#define BCFG1_CFUNOPT 0x80
#define BCFG1_CREQOPT 0x40
#define BCFG1_DMA8 0x10
#define BCFG1_ARBITOPT 0x08
#define BCFG1_PCIMEN 0x04
#define BCFG1_MIOEN 0x02
#define BCFG1_CISDLYEN 0x01
// Bits in RAMBIST registers
#define BISTCMD_TSTPAT5 0x00 //
#define BISTCMD_TSTPATA 0x80 //
#define BISTCMD_TSTERR 0x20 //
#define BISTCMD_TSTPATF 0x18 //
#define BISTCMD_TSTPAT0 0x10 //
#define BISTCMD_TSTMODE 0x04 //
#define BISTCMD_TSTITTX 0x03 //
#define BISTCMD_TSTATRX 0x02 //
#define BISTCMD_TSTATTX 0x01 //
#define BISTCMD_TSTRX 0x00 //
#define BISTSR0_BISTGO 0x01 //
#define BISTSR1_TSTSR 0x01 //
#define BISTSR2_CMDPRTEN 0x02 //
#define BISTSR2_RAMTSTEN 0x01 //
//
// Bits in the I2MCFG EEPROM register
//
#define I2MCFG_BOUNDCTL 0x80
#define I2MCFG_WAITCTL 0x20
#define I2MCFG_SCLOECTL 0x10
#define I2MCFG_WBUSYCTL 0x08
#define I2MCFG_NORETRY 0x04
#define I2MCFG_I2MLDSEQ 0x02
#define I2MCFG_I2CMFAST 0x01
//
// Bits in the I2MCSR EEPROM register
//
#define I2MCSR_EEMW 0x80
#define I2MCSR_EEMR 0x40
#define I2MCSR_AUTOLD 0x08
#define I2MCSR_NACK 0x02
#define I2MCSR_DONE 0x01
//
// Bits in the PMC1 register
//
#define SPS_RST 0x80
#define PCISTIKY 0x40
#define PME_OVR 0x02
//
// Bits in the STICKYHW register
//
#define STICKHW_DS1_SHADOW 0x02
#define STICKHW_DS0_SHADOW 0x01
//
// Bits in the TMCTL register
//
#define TMCTL_TSUSP 0x04
#define TMCTL_TMD 0x02
#define TMCTL_TE 0x01
//
// Bits in the TFTCTL register
//
#define TFTCTL_HWUTSF 0x80 //
#define TFTCTL_TBTTSYNC 0x40
#define TFTCTL_HWUTSFEN 0x20
#define TFTCTL_TSFCNTRRD 0x10 //
#define TFTCTL_TBTTSYNCEN 0x08 //
#define TFTCTL_TSFSYNCEN 0x04 //
#define TFTCTL_TSFCNTRST 0x02 //
#define TFTCTL_TSFCNTREN 0x01 //
//
// Bits in the EnhanceCFG register
//
#define EnCFG_BarkerPream 0x00020000
#define EnCFG_NXTBTTCFPSTR 0x00010000
//#define EnCFG_TXLMT3UPDATE 0x00008000
//#define EnCFG_TXLMT2UPDATE 0x00004000
//#define EnCFG_TXLMT1UPDATE 0x00002000
//#define EnCFG_TXLMT3EN 0x00001000
//#define EnCFG_TXLMT2EN 0x00000800
//#define EnCFG_TXLMT1EN 0x00000400
#define EnCFG_BcnSusClr 0x00000200
#define EnCFG_BcnSusInd 0x00000100
//#define EnCFG_CWOFF1 0x00000080
#define EnCFG_CFP_ProtectEn 0x00000040
#define EnCFG_ProtectMd 0x00000020
#define EnCFG_HwParCFP 0x00000010
//#define EnCFG_QOS 0x00000008
#define EnCFG_CFNULRSP 0x00000004
#define EnCFG_BBType_MASK 0x00000003
#define EnCFG_BBType_g 0x00000002
#define EnCFG_BBType_b 0x00000001
#define EnCFG_BBType_a 0x00000000
//
// Bits in the Page1Sel register
//
#define PAGE1_SEL 0x01
//
// Bits in the CFG register
//
#define CFG_TKIPOPT 0x80
#define CFG_RXDMAOPT 0x40
#define CFG_TMOT_SW 0x20
#define CFG_TMOT_HWLONG 0x10
#define CFG_TMOT_HW 0x00
#define CFG_CFPENDOPT 0x08
#define CFG_BCNSUSEN 0x04
#define CFG_NOTXTIMEOUT 0x02
#define CFG_NOBUFOPT 0x01
//
// Bits in the TEST register
//
#define TEST_LBEXT 0x80 //
#define TEST_LBINT 0x40 //
#define TEST_LBNONE 0x00 //
#define TEST_SOFTINT 0x20 //
#define TEST_CONTTX 0x10 //
#define TEST_TXPE 0x08 //
#define TEST_NAVDIS 0x04 //
#define TEST_NOCTS 0x02 //
#define TEST_NOACK 0x01 //
//
// Bits in the HOSTCR register
//
#define HOSTCR_TXONST 0x80 //
#define HOSTCR_RXONST 0x40 //
#define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
#define HOSTCR_AP 0x10 // Port Type 1 = AP
#define HOSTCR_TXON 0x08 //0000 1000
#define HOSTCR_RXON 0x04 //0000 0100
#define HOSTCR_MACEN 0x02 //0000 0010
#define HOSTCR_SOFTRST 0x01 //0000 0001
//
// Bits in the MACCR register
//
#define MACCR_SYNCFLUSHOK 0x04 //
#define MACCR_SYNCFLUSH 0x02 //
#define MACCR_CLRNAV 0x01 //
//
// Bits in the RCR register
//
#define RCR_SSID 0x80
#define RCR_RXALLTYPE 0x40 //
#define RCR_UNICAST 0x20 //
#define RCR_BROADCAST 0x10 //
#define RCR_MULTICAST 0x08 //
#define RCR_WPAERR 0x04 //
#define RCR_ERRCRC 0x02 //
#define RCR_BSSID 0x01 //
//
// Bits in the TCR register
//
#define TCR_SYNCDCFOPT 0x02 //
#define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
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