ps110.vhd

bpsk信号调制

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ps110 is
port(
clk:in std_logic;
en1:in std_logic;--ps data and pw data;
en2:in std_logic;--time data;

 --q1:buffer std_logic_vector(5 downto 0);
din:in std_logic_vector(15 downto 0);
dout:out std_logic);
end ps110;
architecture behav of ps110 is
signal psd:std_logic_vector(9 downto 0);
signal pwd:std_logic_vector(5 downto 0);
signal tmd:std_logic_vector(5 downto 0);

signal temp:std_logic_vector(9 downto 0);
signal q1,q2:std_logic_vector(5 downto 0);

signal clkpw:std_logic;
begin

process(en1)
begin
if(en1='1')then 
psd<=din(15 downto 6);
pwd<=din(5 downto 0);
end if;
end process;

process(en2)
begin
if(en2='1')then
tmd<=din(5 downto 0);

end if;
end process;

process(en2,clk)
--variable q1:std_logic_vector(5 downto 0);
begin
if(en2='1')then
q1<="000000";
clkpw<='0';
elsif(clk'event and clk='1')then
if(q1<('0'&pwd(5 downto 1))) then clkpw<='1';q1<=q1+1;
elsif(q1=pwd-1)then clkpw<='0';q1<="000000";
else clkpw<='0'; q1<=q1+1;
end if;
end if;
end process;

process(clkpw,psd,tmd)
--variable q2:std_logic_vector(5 downto 0);
begin
if(en2='1')then
   q2<="000000";
elsif(clkpw'event and clkpw='1')then
if(q2="000000") then 
temp<=psd;
q2<=q2+1;
elsif(q2<"001011")  then
  temp(9 downto 1)<=temp(8 downto 0);
 -- dout<=temp(9);
  q2<=q2+1;
  temp(0)<='0';
 elsif(q2=tmd+"001001")then
    dout<='0';
    q2<="000000";
 else 
   dout<='0';
   q2<=q2+1;
   end if;   dout<=temp(9);
   end if;
  
   end process;
   
   end behav;
 
  
--(q2<(tmd+"001010"))