uarttest.tan.rpt

FPGA模拟UART

; N/A   ; None         ; 6.100 ns   ; 74165:inst9|98                                   ; TXD    ; BaudRateMul4 ;
; N/A   ; None         ; 3.100 ns   ; inst19                                           ; RI     ; BaudRateMul4 ;
+-------+--------------+------------+--------------------------------------------------+--------+--------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+------+----------------+--------------+
; Minimum Slack ; Required th ; Actual th ; From ; To             ; To Clock     ;
+---------------+-------------+-----------+------+----------------+--------------+
; N/A           ; None        ; 8.300 ns  ; RXD  ; 74164:inst69|3 ; BaudRateMul4 ;
+---------------+-------------+-----------+------+----------------+--------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon Dec 08 12:28:37 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UartTest -c UartTest
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "RXD" is an undefined clock
    Info: Assuming node "BaudRateMul4" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "COUNT4:inst3|SYNTHESIZED_WIRE_2_synthesized_var" as buffer
    Info: Detected ripple clock "COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var" as buffer
    Info: Detected ripple clock "74164:inst70|3" as buffer
Info: No valid register-to-register data paths exist for clock "RXD"
Info: Can't find any paths of type Clock between source node "BaudRateMul4" and destination node "74164:inst69|6"
Info: Clock "BaudRateMul4" has Internal fmax of 80.65 MHz between source register "74164:inst69|6" and destination register "74377:inst54|35" (period= 12.4 ns)
    Info: + Longest register to register delay is 2.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC31; Fanout = 2; REG Node = '74164:inst69|6'
        Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 2.500 ns; Loc. = LC17; Fanout = 1; REG Node = '74377:inst54|35'
        Info: Total cell delay = 1.500 ns ( 60.00 % )
        Info: Total interconnect delay = 1.000 ns ( 40.00 % )
    Info: - Smallest clock skew is -7.900 ns
        Info: + Shortest clock path from clock "BaudRateMul4" to destination register is 2.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'
            Info: 2: + IC(0.700 ns) + CELL(1.200 ns) = 2.900 ns; Loc. = LC17; Fanout = 1; REG Node = '74377:inst54|35'
            Info: Total cell delay = 2.200 ns ( 75.86 % )
            Info: Total interconnect delay = 0.700 ns ( 24.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 1.300 ns
Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock "BaudRateMul4" with clock skew larger than data delay. See Compilation Report for details.
Info: Can't find any paths of type Clock between source node "BaudRateMul4" and destination node "74164:inst69|10"
Info: Found hold time violation between source  pin or register "74164:inst69|9" and destination pin or register "74164:inst69|10" for clock "BaudRateMul4" (Hold time is 3.6 ns)
    Info: + Largest clock skew is 6.200 ns
        Info: - Shortest clock path from clock "BaudRateMul4" to source register is 4.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'
            Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 2.300 ns; Loc. = LC11; Fanout = 10; REG Node = 'COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var'
            Info: 3: + IC(1.100 ns) + CELL(1.200 ns) = 4.600 ns; Loc. = LC24; Fanout = 2; REG Node = '74164:inst69|9'
            Info: Total cell delay = 3.500 ns ( 76.09 % )
            Info: Total interconnect delay = 1.100 ns ( 23.91 % )
    Info: - Micro clock to output delay of source is 0.700 ns
    Info: - Shortest register to register delay is 2.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC24; Fanout = 2; REG Node = '74164:inst69|9'
        Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 2.500 ns; Loc. = LC37; Fanout = 2; REG Node = '74164:inst69|10'
        Info: Total cell delay = 1.500 ns ( 60.00 % )
        Info: Total interconnect delay = 1.000 ns ( 40.00 % )
    Info: + Micro hold delay of destination is 0.600 ns
Info: tsu for register "74164:inst69|3" (data pin = "RXD", clock pin = "BaudRateMul4") is -0.200 ns
    Info: + Longest pin to register delay is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'RXD'
        Info: 2: + IC(0.600 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC34; Fanout = 2; REG Node = '74164:inst69|3'
        Info: Total cell delay = 2.500 ns ( 80.65 % )
        Info: Total interconnect delay = 0.600 ns ( 19.35 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "BaudRateMul4" to destination register is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 2.300 ns; Loc. = LC11; Fanout = 10; REG Node = 'COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var'
        Info: 3: + IC(1.100 ns) + CELL(1.200 ns) = 4.600 ns; Loc. = LC34; Fanout = 2; REG Node = '74164:inst69|3'
        Info: Total cell delay = 3.500 ns ( 76.09 % )
        Info: Total interconnect delay = 1.100 ns ( 23.91 % )
Info: Can't find any paths of type Clock between source node "BaudRateMul4" and destination node "74377:inst54|28"
Info: Can't find any paths of type TCO between source node "BaudRateMul4" and destination node "RxdD0p"
Info: Can't find any paths of type Clock between source node "BaudRateMul4" and destination node "74164:inst69|3"
Info: th for register "74164:inst69|3" (data pin = "RXD", clock pin = "BaudRateMul4") is 8.300 ns
    Info: + Micro hold delay of destination is 0.600 ns
    Info: - Shortest pin to register delay is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_2; Fanout = 2; CLK Node = 'RXD'
        Info: 2: + IC(0.600 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC34; Fanout = 2; REG Node = '74164:inst69|3'
        Info: Total cell delay = 2.500 ns ( 80.65 % )
        Info: Total interconnect delay = 0.600 ns ( 19.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Mon Dec 08 12:28:38 2008
    Info: Elapsed time: 00:00:01