prev_cmp_count4.tan.qmsg

FPGA模拟UART

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register inst1 register inst1 227.27 MHz 4.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 227.27 MHz between source register \"inst1\" and destination register \"inst1\" (period= 4.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns + Longest register register " "Info: + Longest register to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst1 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inst1 inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 100.00 % ) " "Info: Total cell delay = 2.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inst1 inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inst1 {} inst1 {} } { 0.000ns 0.000ns } { 0.000ns 2.400ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 112 208 376 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 112 208 376 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inst1 inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inst1 {} inst1 {} } { 0.000ns 0.000ns } { 0.000ns 2.400ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "inst1 RI CLK 2.000 ns register " "Info: tsu for register \"inst1\" (data pin = \"RI\", clock pin = \"CLK\") is 2.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.200 ns + Longest pin register " "Info: + Longest pin to register delay is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns RI 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'RI'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RI } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 96 208 376 112 "RI" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.600 ns) 2.200 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.900 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { RI inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 59.09 % ) " "Info: Total cell delay = 1.300 ns ( 59.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 40.91 % ) " "Info: Total interconnect delay = 0.900 ns ( 40.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { RI inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { RI {} RI~out {} inst1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 112 208 376 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { RI inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { RI {} RI~out {} inst1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[3\] inst4 3.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[3\]\" through register \"inst4\" is 3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 112 208 376 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns inst4 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = 'inst4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK inst4 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 488 456 520 568 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst4 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 488 456 520 568 "inst4" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.800 ns + Longest register pin " "Info: + Longest register to pin delay is 0.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst4 1 REG LC5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'inst4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst4 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 488 456 520 568 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns Q\[3\] 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'Q\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { inst4 Q[3] } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 96 704 880 112 "Q\[0\]" "" } { 232 704 880 248 "Q\[1\]" "" } { 368 704 880 384 "Q\[2\]" "" } { 504 704 880 520 "Q\[3\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 100.00 % ) " "Info: Total cell delay = 0.800 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { inst4 Q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.800 ns" { inst4 {} Q[3] {} } { 0.000ns 0.000ns } { 0.000ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst4 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst4 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { inst4 Q[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.800 ns" { inst4 {} Q[3] {} } { 0.000ns 0.000ns } { 0.000ns 0.800ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "inst1 RI CLK -0.100 ns register " "Info: th for register \"inst1\" (data pin = \"RI\", clock pin = \"CLK\") is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns CLK 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 112 208 376 128 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.500 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.500 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { CLK inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 0.700 ns RI 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.700 ns) = 0.700 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'RI'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RI } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 96 208 376 112 "RI" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.600 ns) 2.200 ns inst1 2 REG LC1 5 " "Info: 2: + IC(0.900 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC1; Fanout = 5; REG Node = 'inst1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { RI inst1 } "NODE_NAME" } } { "COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { { 80 456 520 160 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns ( 59.09 % ) " "Info: Total cell delay = 1.300 ns ( 59.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 40.91 % ) " "Info: Total interconnect delay = 0.900 ns ( 40.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { RI inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { RI {} RI~out {} inst1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.500 ns" { CLK {} CLK~out {} inst1 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.900ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { RI inst1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.200 ns" { RI {} RI~out {} inst1 {} } { 0.000ns 0.000ns 0.900ns } { 0.000ns 0.700ns 0.600ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 06 13:56:11 2008 " "Info: Processing ended: Sat Dec 06 13:56:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}