count4.map.qmsg

FPGA模拟UART

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create VHDL File Quartus II " "Info: Running Quartus II Create VHDL File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 06 13:57:40 2008 " "Info: Processing started: Sat Dec 06 13:57:40 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off COUNT4 -c COUNT4 --convert_bdf_to_vhdl=D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off COUNT4 -c COUNT4 --convert_bdf_to_vhdl=D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COUNT4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file COUNT4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 COUNT4 " "Info: Found entity 1: COUNT4" {  } { { "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" " " "Info: Elaborating entity \"\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "COUNT4 " "Warning: Processing legacy GDF or BDF entity \"COUNT4\" with Max+Plus II bus and instance naming rules" {  } { { "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" "" { Schematic "D:/项目/断针主机/cpld/2/UartTest/COUNT4.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create VHDL File 0 s 1  Quartus II " "Info: Quartus II Create VHDL File was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 06 13:57:40 2008 " "Info: Processing ended: Sat Dec 06 13:57:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}