uarttest.map.qmsg

FPGA模拟UART

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create VHDL File Quartus II " "Info: Running Quartus II Create VHDL File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 08 12:30:07 2008 " "Info: Processing started: Mon Dec 08 12:30:07 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UartTest -c UartTest --convert_bdf_to_vhdl=D:/TMP/UartTest/UartTest.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UartTest -c UartTest --convert_bdf_to_vhdl=D:/TMP/UartTest/UartTest.bdf" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UartTest.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file UartTest.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 UartTest " "Info: Found entity 1: UartTest" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" " " "Info: Elaborating entity \"\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst5 " "Warning: Block or symbol \"NOT\" of instance \"inst5\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 616 552 600 648 "inst5" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst71 " "Warning: Block or symbol \"NOT\" of instance \"inst71\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1248 784 832 1280 "inst71" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst73 " "Warning: Block or symbol \"NOT\" of instance \"inst73\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1280 784 832 1312 "inst73" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst75 " "Warning: Block or symbol \"NOT\" of instance \"inst75\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1312 784 832 1344 "inst75" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst77 " "Warning: Block or symbol \"NOT\" of instance \"inst77\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1344 784 832 1376 "inst77" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst8 " "Warning: Block or symbol \"NOT\" of instance \"inst8\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 648 552 600 680 "inst8" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst13 " "Warning: Block or symbol \"NOT\" of instance \"inst13\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 680 552 600 712 "inst13" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst15 " "Warning: Block or symbol \"NOT\" of instance \"inst15\" overlaps another block or symbol" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 712 552 600 744 "inst15" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "" 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74377 " "Warning: Found Altera-specific megafunction, primitive or component \"74377\"" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1736 656 760 1928 "inst54" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74164 " "Warning: Found Altera-specific megafunction, primitive or component \"74164\"" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1240 616 736 1416 "inst69" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74165 " "Warning: Found Altera-specific megafunction, primitive or component \"74165\"" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 352 752 872 576 "inst7" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74164 " "Warning: Found Altera-specific megafunction, primitive or component \"74164\"" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1448 616 736 1624 "inst70" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_IS_MEGAFUNCTION" "74165 " "Warning: Found Altera-specific megafunction, primitive or component \"74165\"" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 608 752 872 832 "inst9" "" } } } }  } 0 0 "Found Altera-specific megafunction, primitive or component \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74164_1 " "Warning: Design name for \"74164_1\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0 "" 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74164_3 " "Warning: Design name for \"74164_3\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0 "" 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74165_2 " "Warning: Design name for \"74165_2\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0 "" 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74165_4 " "Warning: Design name for \"74165_4\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0 "" 0}
{ "Warning" "WGDFX_DESIGN_NAME_CONTAIN_NUMBER" "74377_0 " "Warning: Design name for \"74377_0\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" {  } { { "D:/TMP/UartTest/UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { } } }  } 0 0 "Design name for \"%1!s!\" contains a number -- illegal for Verilog HDL and VHDL -- adding \"\\\" in front of name" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create VHDL File 0 s 18 s Quartus II " "Info: Quartus II Create VHDL File was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 08 12:30:07 2008 " "Info: Processing ended: Mon Dec 08 12:30:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}