prev_cmp_uarttest.tan.qmsg

FPGA模拟UART

{ "Info" "ITDB_TSU_RESULT" "74164:inst69\|3 RXD BaudRateMul4 -0.300 ns register " "Info: tsu for register \"74164:inst69\|3\" (data pin = \"RXD\", clock pin = \"BaudRateMul4\") is -0.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns + Longest pin register " "Info: + Longest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns RXD 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'RXD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1240 392 560 1256 "RXD" "" } { 1280 392 456 1296 "RXD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.500 ns) 3.100 ns 74164:inst69\|3 2 REG LC14 2 " "Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC14; Fanout = 2; REG Node = '74164:inst69\|3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 67.74 % ) " "Info: Total cell delay = 2.100 ns ( 67.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 32.26 % ) " "Info: Total interconnect delay = 1.000 ns ( 32.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { RXD {} RXD~out {} 74164:inst69|3 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BaudRateMul4 destination 4.700 ns - Shortest register " "Info: - Shortest clock path from clock \"BaudRateMul4\" to destination register is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns BaudRateMul4 1 CLK PIN_43 13 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 13; CLK Node = 'BaudRateMul4'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { BaudRateMul4 } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 320 432 600 336 "BaudRateMul4" "" } { 1512 1160 1304 1528 "BaudRateMul4" "" } { 1896 912 1014 1912 "BaudRateMul4" "" } { 272 432 736 288 "BaudRateMul4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 2.300 ns COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var 2 REG LC11 10 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 2.300 ns; Loc. = LC11; Fanout = 10; REG Node = 'COUNT4:inst25\|SYNTHESIZED_WIRE_2_synthesized_var'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var } "NODE_NAME" } } { "COUNT4.vhd" "" { Text "D:/TMP/UartTest/COUNT4.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.200 ns) 4.700 ns 74164:inst69\|3 3 REG LC14 2 " "Info: 3: + IC(1.200 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC14; Fanout = 2; REG Node = '74164:inst69\|3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|3 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 74.47 % ) " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 25.53 % ) " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { BaudRateMul4 {} BaudRateMul4~out {} COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var {} 74164:inst69|3 {} } { 0.000ns 0.000ns 0.000ns 1.200ns } { 0.000ns 1.000ns 1.300ns 1.200ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { RXD {} RXD~out {} 74164:inst69|3 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 1.500ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { BaudRateMul4 COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { BaudRateMul4 {} BaudRateMul4~out {} COUNT4:inst25|SYNTHESIZED_WIRE_2_synthesized_var {} 74164:inst69|3 {} } { 0.000ns 0.000ns 0.000ns 1.200ns } { 0.000ns 1.000ns 1.300ns 1.200ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "Clock BaudRateMul4 74377:inst54\|28 " "Info: Can't find any paths of type Clock between source node \"BaudRateMul4\" and destination node \"74377:inst54\|28\"" {  } {  } 0 0 "Can't find any paths of type %1!s! between source node \"%2!s!\" and destination node \"%3!s!\"" 0 0 "" 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "TCO BaudRateMul4 RxdD0p " "Info: Can't find any paths of type TCO between source node \"BaudRateMul4\" and destination node \"RxdD0p\"" {  } {  } 0 0 "Can't find any paths of type %1!s! between source node \"%2!s!\" and destination node \"%3!s!\"" 0 0 "" 0}
{ "Info" "ITDB_PATH_NOT_FOUND" "Clock BaudRateMul4 74164:inst69\|3 " "Info: Can't find any paths of type Clock between source node \"BaudRateMul4\" and destination node \"74164:inst69\|3\"" {  } {  } 0 0 "Can't find any paths of type %1!s! between source node \"%2!s!\" and destination node \"%3!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "74164:inst69\|3 RXD BaudRateMul4 8.400 ns register " "Info: th for register \"74164:inst69\|3\" (data pin = \"RXD\", clock pin = \"BaudRateMul4\") is 8.400 ns" { { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns RXD 1 CLK PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = PIN_37; Fanout = 2; CLK Node = 'RXD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "UartTest.bdf" "" { Schematic "D:/TMP/UartTest/UartTest.bdf" { { 1240 392 560 1256 "RXD" "" } { 1280 392 456 1296 "RXD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.500 ns) 3.100 ns 74164:inst69\|3 2 REG LC14 2 " "Info: 2: + IC(1.000 ns) + CELL(1.500 ns) = 3.100 ns; Loc. = LC14; Fanout = 2; REG Node = '74164:inst69\|3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "74164.bdf" "" { Schematic "c:/altera/72/quartus/libraries/others/maxplus2/74164.bdf" { { 56 360 424 136 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 67.74 % ) " "Info: Total cell delay = 2.100 ns ( 67.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 32.26 % ) " "Info: Total interconnect delay = 1.000 ns ( 32.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { RXD {} RXD~out {} 74164:inst69|3 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { RXD 74164:inst69|3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { RXD {} RXD~out {} 74164:inst69|3 {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.600ns 1.500ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 08 12:27:58 2008 " "Info: Processing ended: Mon Dec 08 12:27:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}